Akash Raj Verma — CTO
Worked on • PCIe Gen6 - Physical Layer (Flit Mode + Non-Flit Mode) Functional Verification using Palladium Z1 Emulator - L0p Verification - Test vPlan using vManager, Feature Verification. • PCIe Gen5 - Functional Verification using Palladium Z1 Emulator - Created Emulation friendly tests for Physical Layer Features - Link Speed , Link Width, compliance, Loopback, Traffic test etc. • USB 3.2 Link Layer feature verification - Loopback & Compliance. • USB 2.0 Low Power Feature Verification. Competencies • Knowledge : Digital Electronics, OOP, STA Basics, UVM Basics • Languages : Verilog, SystemVerilog, C, C++ • Scripting : TCL, Bash • Protocol : PCIe 5.0, PCIe 6.0, USB3.2, USB2.0, AMBA APB, I2C • Tools and OS : xCelium, vManager, Jenkins, QuestaSim, Xcelium, Palladium Z1
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in PCIe and USB protocols.
Location: Delhi, India
Experience: 4 yrs 9 mos
Skills
- Functional Verification
- Pcie
Career Highlights
- Expert in PCIe and USB functional verification.
- Proficient in using Palladium Z1 Emulator for verification.
- Strong foundation in digital electronics and verification methodologies.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Lead Member of Technical Staff (2 yrs 1 mo)
Cadence Design Systems
Design Engineer (2 yrs 8 mos)
Design Engineering Intern (10 mos)
Education
Master of Technology - MTech at C - DAC, NOIDA
Bachelor of Technology (BTech) at Netaji Subhas University of Technology, East Campus
at Greenfields Public School
