Anindya Pramanik — Product Engineer

A dedicated RTL Design Engineer focused on the development of complex, high-speed digital logic for ASIC platforms. My expertise is rooted in architecting robust, synthesizable SystemVerilog/Verilog and ensuring quality through rigorous upfront verification. Core Implementation & Sign-off Competencies: Synthesis: Translating RTL into optimized gate-level netlists targeting PPA (Power, Performance, Area). Formal Verification: Utilizing Lint for early code quality checks and LEC (Logical Equivalence Checking) to ensure logical integrity post-synthesis and netlist modification. Design Robustness: Expert in CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and mitigation, ensuring synchronous and asynchronous boundaries are safe and reliable. I am committed to achieving first-pass silicon success by maintaining clean code and executing a methodical flow from micro-architecture definition to tape-out preparation. Always eager to contribute to cutting-edge projects in high-speed networking and AI acceleration.

Stackforce AI infers this person is a Digital IC Design Engineer with expertise in RTL design and verification.

Location: Ghaziabad, Uttar Pradesh, India

Experience: 0 mo