Anirban Ghosh

Product Manager

Bengaluru, Karnataka, India21 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SoC design and verification.
Led multiple high-impact ASIC projects at NVIDIA.
Strong background in RTL and u-Arch design.

Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in SoC architecture.

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Skills

Core Skills

SocDesign VerificationFunctional SafetyIp DesignRtl DesignU-arch DesignPhysical DesignClock Domain Crossing AnalysisDesign SynthesisRtl OptimizationVideo Decoder Ip DevelopmentArm ArchitectureRtl ModellingMemory ModellingDebuggingMaintenance

Other Skills

AMBA AHBARMASICApplication-Specific Integrated Circuits (ASIC)Bus Protocol UnderstandingEDAFMEA AnalysisHigh Speed JESD204 IO ControllerICIntegrated Circuits (IC)Logic SynthesisLow Power ManagementPLC ProgrammingPerlPerl Scripting

Experience

21 yrs 11 mos

Total Experience

3 yrs 7 mos

Average Tenure

14 yrs 7 mos

Current Experience

Nvidia

3 roles

Sr Manager, ASIC Design

Promoted

Jun 2021 – Present · 5 yrs

Managing Tegra SOC Safety Island, Boot Power Management Sub-System, ARM/RISCV based CPU Sub-System, Low Power Management HW IP(s) design/verification activities

SoCARMLow Power ManagementDesign Verification

Manager, ASIC Design

Promoted

Apr 2019 – May 2021 · 2 yrs 1 mo

Managed ASILD rated Functional Safety Island, ARM CPU Sub-System IP design/verification for Tegra automotive SOC.
Managed High Speed JESD204 IO controller (32GB/s Bandwidth) IP design/verification for Tegra SOC.

Functional SafetyIP DesignHigh Speed JESD204 IO Controller

Senior ASIC Engineer

Sep 2011 – Mar 2019 · 7 yrs 6 mos

Involved in development of NVidia Application Processor SOC (Tegra) used by Automotive/Game-Console/Tablets.
u-Arch & RTL Design for SOC IP units;
u-Arch & RTL Design for AXI/APB Interconnect, DMA Engines;
u-Arch & RTL Design for Graphics HOST/Multi-media Sub-system Interconnect;
u-Arch & RTL Design for GPIO (General Purpose IO controllers);
Wire Reduction Design Methodology for Interconnect;
Security Concepts in SOC; TZ Security etc.;
Multiple Guest OS-level Virtualization for HW resources, Hypervisor for Automotive (IVI) Applications;
Inter-OS & Intra-OS protection of HW resources;
Inter-SW application(s) protection of HW resources;
Closure of SW Programming Model with multiple teams;
Safety Related FMEA analysis for SOC components for ADAS applications;
Safety Aware Design for Interconnect, DMA engines for ADAS applications;
Drive Unit Verification Team technically;
Testplan review, System Level failure debug, Post-silicon debugs;
Synthesis/Netlist Related Issues Handling, CDC, MTBF Analysis, Review;
Floor plan Closure with PD team;
Congestion & Power Aware RTL Design;
Working closely with PD team for Timing sign-off for 16ff, 20nm etc.

u-Arch DesignRTL DesignSecurity ConceptsFMEA Analysis

Amd

MTS Silicon Design Engineer

Mar 2011 – Aug 2011 · 5 mos · Bangalore

Involved in AMD's client fusion product development for laptop/notebook processor SoC.
1. Custom physical design in 32 nm - writing netlist/hand placement of cells
2. Full-Chip Clock Domanin Crossing(CDC) Analysis in Netlist Level
3. Race Detection/Glitch Analysis of SoC level false paths/max delay paths/multi-cylce paths
4. MTBF/FIT calculation of SoC level Synchronizer cells in design(back-2-back Synchronizers)
5. Same clock domain false path marker analysis
6. Full-Chip Scan Timing Analysis for IP interfaces

Physical DesignClock Domain Crossing AnalysisRace Detection

Magma design automation

Senior Member of Technical Staff

Nov 2006 – Mar 2011 · 4 yrs 4 mos · Bengaluru, Karnataka, India

Involved in Blast Create/Talus Design Synthesis Tool Development.
1. DesignWare(DW) Component Development & Maintenance - DW01/DW02/DW03/DW04/DW05/DW06 library development for Magma Synthesis Tool
2. Datapath elements design/verification i.e. Verilog/VHDL-based IP design
3. RTL Optimization - Sharing/Un-Sharing, MUX optimization, Comparator
4. Timing Driven Datapath Synthesis - Expression Grouping using Carry-Save concepts, Adder Architecture Switching, Adder Cloning
5. Simulation Model development for Carry-Save Components
6. Contributed in Module Generator(MG)
7. QOR Analysis/BenchMark of Customer Designs
8. Formal Failure Debug/Test Case Reduction

Design SynthesisRTL OptimizationTiming Driven Datapath Synthesis

Conexant systems india

Senior Design Engg

Jun 2006 – Oct 2006 · 4 mos · Greater Hyderabad Area

Involved in Video Decoder IP development.
1. Understanding of ARM based Video decoder environment
2. Multi-Stream & Multi-format Video Decoder (H.264/MPEG/VC-1D)
3. Understanding of Internal Architectures/Bus Protocol (AMBA - AHB, AXI)

Video Decoder IP DevelopmentARM ArchitectureBus Protocol Understanding

Softjin technologies

Design Engineer

Feb 2005 – May 2006 · 1 yr 3 mos · Bengaluru, Karnataka, India

Worked in ODC of Tharas Systems Inc, USA for Tharas Hammer-based H/W assisted verification.
1. Hammer Accelerated RTL modelling
2. RTL Modelling for DesignWare Components in Verilog
3. Gate Count Analysis of DW Models with respect to Design Compiler
4. IBM/Virage/Artisan SRAM Memory Model Development in Verilog2K
5. Perl Scripting for automatic generation of memory models with verilog wrapper
6. Micron DDR2 memory modelling
7. DDR2 protocols

RTL ModellingPerl ScriptingMemory Modelling

Samtel

Graduate Engineer Trainee(GET 2003 batch)

Aug 2003 – Aug 2004 · 1 yr · India

Involved in maintenance of Factory machines used in Television Picture Tube Assembly Line.
1. Debugging of breakdown machines understanding circuit diagrams
2. Repairing of PCB's containing OPAMPs, transistors, Intel 8255 pheripheral IC, etc
3. Programmable Logic Controller(PLC) programming for Automatic conveyers for Mitsubishi/Siemens/OMRON PLC
4. Installation of 2 New machines in Assembly Line and trained Diploma/ITI engineers on the usage/maintenance part

DebuggingPLC ProgrammingMaintenance