A

Ankit sharma

Software Engineer

Delhi, India4 yrs 2 mos experience

Key Highlights

  • Expert in Analog and Mixed Layout design across multiple technology nodes.
  • Hands-on experience with Cadence Virtuoso and EDA tools.
  • Strong understanding of VLSI fabrication and analog electronics.
Stackforce AI infers this person is a VLSI design engineer with expertise in analog and mixed-signal circuits.

Contact

Skills

Core Skills

Cadence VirtuosoPhysical VerificationAnalog LayoutsStandard Cells

Other Skills

Layout Versus Schematic (LVS)Design Rule Checking (DRC)Cadence Virtuoso Layout EditorAnalog CircuitsDigital ElectronicsEDA ToolsVLSI FabricationSimulation of Logic GatesControl SystemC (Programming Language)

About

Analog and Mixed Layout design engineer with experience across different technology nodes such as TSMC 2nm, 3nm, 4nm, 5nm, 7nm, 16nm and 28nm. Have hands on experience on EDA tools and sound understanding of - > VLSI fabrication, Analog electronics, Digital electronics, network , RC circuit. > Simulation of logic gates using Ltspice. > Proficiency in using EDA tools - Cadence Virtuoso layout editor L ,XL and verification flows - mentor graphics calibre, > Understanding of concepts like Latch-up, Antenna effect, EM. > Knowledge of matching of MOSFETS , Resistors and Capacitors. > Worked on standard cells, Analog layouts in 28nm. > Basic understanding of finfet technology in 16nm. > Worked on standard cells, high density standard cells in 16nm. >Worked on full custom standard cells in 7nm. >Worked on blocks like BGR, POWERAMP, TEST_LOGIC and PROTECTION_OUT in 7nm. > Good understanding of PEX , DRC and LVS.

Experience

4 yrs 2 mos
Total Experience
2 yrs 3 mos
Average Tenure
1 yr 11 mos
Current Experience

Synopsys inc

Layout design Sr Engineer

Jul 2024Present · 1 yr 11 mos · Bengaluru, Karnataka, India · Hybrid

Physical VerificationCadence VirtuosoLayout Versus Schematic (LVS)Design Rule Checking (DRC)Cadence Virtuoso Layout EditorAnalog Circuits+1

Signoff semiconductors

Design Engineer - I - AMS layout

Jan 2022Apr 2024 · 2 yrs 3 mos · Hyderabad, Telangana, India · On-site

Analog LayoutsStandard CellsEDA ToolsVLSI FabricationSimulation of Logic Gates

Education

Chatrapati Sahuji Maharaj Kanpur University, Kanpur

Bachelor of Technology - BTech — Electronics and communication

Aug 2016Sep 2020

DAV public school saharanpur

Intermediate — PCM

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