Dec 2017 – Jun 2018 · 6 mos

• In this role, I was responsible for leading one of the partitions with a sub partition which had multi clocks & multi-power domains from netlist to GDS on 7nm technology process. The design was critical on congestion, Power, IR, DRC and Timing and had worked closely with cross functional teams to deliver GDS with best PPA.
• Tools worked on : FV, CLP, Calibre, Redhawk, ICC2, EDI & PT

Jul 2016 – Nov 2017 · 1 yr 4 mos

• For my first project, I was responsible for FV, CLP and IR analysis for Multimedia Display subsystem (MDSS) for one of the premier tier SD chip.
• For my next project, I was responsible for closing one of the partitions in MDSS which was critical on IR, timing and congestion along with the responsibilities from previous project.
• Tools worked on : FV, CLP, Redhawk, Calibre & ICC2

May 2015 – Jul 2015 · 2 mos · Bengaluru, Karnataka, India

• In this role, I was mainly responsible for developing scripts in Perl and TCL to automate the PD flow