Ashok Vijayarangam — CEO
Over 25+ Years of Industrial Experience in the field of VLSI. Responsibilities include architecting the verification environment for complex SOC. Implementing the Verification Environment using Verilog/ System Verilog/ VMM/ AVM/ OVM/ UVM Methodologies. Implementation of verification environment with pure class or pure module or hybrid models experience for complex SOC using AVM. Involved in verification closure of blocks/chips and SOC. Familiarity with Pre-Si/Post-Si verification methodology. Experience in Functional Verification which includes knowledge in test plan, Functional coverage, code coverage, exclusion files, test writing, regression handling, test debugging and scripting. Generating the VMM RAL Model and integrating them into the ASIC Flow/Environment. Generating the Sequence Library Package and Virtual Sequences while delivering the VIP for client. Implementing the Layered Sequences approach based on the Application requirement. Fixing the Arbitration scheme for the Sequencer. Knowledge on setting up the Register Layer / TLMs/ Factory & Configuration / Taking proper care of the sequences and Feeding them in UVM. Experience in High speed multi-gigabit serial interface (SerDes) PMD Digital Module. Knowledge of Gigabit Ethernet (GBE) PHYs including the 40GbE and 100GbE Standards. Intense knowledge in IEEE802.3 Ethernet Standards. Most closely worked on clauses 72 (startup protocol for 10GBASE-KR Module), Clause 93(startup protocol for 100GBASE-KR4 PMD module), Clause 22 (MDIO Interface) and Clause 45 (Extension of MDIO for 10GbE Networks) of Ethernet Standards. Intense knowledge in VMM/ OVM/ UVM Advanced concepts which is used for building the verification environment to validate the Functionality of complex chipset. Knowledge in Assertion Based Verification (ABV) in front end ASIC flow using SVA (System Verilog Assertions)
Stackforce AI infers this person is a Telecommunications and Semiconductor expert with extensive experience in VLSI and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 24 yrs 3 mos
Skills
- High Speed Multi-gigabit Serial Interface (serdes)
- Uvm
- Verification Environment
- Functional Verification
- Pcie
- Fpga
- Automated Testing
Career Highlights
- Over 25 years of experience in VLSI design and verification.
- Expertise in architecting complex SOC verification environments.
- Strong background in Ethernet standards and protocols.
Work Experience
Intel Corporation
Senior Manager - SoC Design Engineering (4 yrs 3 mos)
Manager - SOC Design Engineering (1 yr 5 mos)
Manager of iCDG Group (2 yrs 6 mos)
Broadcom
Principal Engineer (7 yrs 4 mos)
Xilinx
Verification Lead (5 yrs 3 mos)
DRDO, Centre for Airborne Systems
Scientist B (3 yrs 6 mos)
Education
B.Tech (Distinction) at Pondicherry University
at Don Bosco Matriculation School
