Bhargav Br — Software Engineer
Technology nodes worked on ; 6nm,16nm,90nm,130nm Process Knowledge : TSMC,Intel Transistor Technologies ; MosFET,FinFET Developing mixed signal CMOS IC layout design at block level ,Floor planning and Integration,deriving block constraints from design requirements. Having better understanding of Finfets & Double patterning,Good understanding of analog layout Techniques such as device matching ,shielding etc. Designing an area efficient & parasitic aware block layout Running checkers like Totem RV (Em/IR drop), PERC,DRC,LVS,ERC,HV DRC, extraction, density fixes,Antenna on block as well as Top-level design and post layout extraction ,Finally signing off a physically verified layout. Tool knowledge : cadence virtuoso schematic and layout editor and custom complier physical verification: Calibre,ICV,Assura Having Good communication skills and ability to work independently.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog Layout and Physical Verification.
Location: Bengaluru, Karnataka, India
Experience: 0 mo
Skills
- Analog Layout
- Mixed Signal Cmos Ic Layout Design
Career Highlights
- Expert in mixed signal CMOS IC layout design.
- Proficient in physical verification tools like Calibre and ICV.
- Strong understanding of FinFET and analog layout techniques.
Work Experience
SumedhaIT
Analog Layout trainee (3 mos)
Education
Bachelor of Technology - BTech at Rajeev gandhi memorial college of engineering and technology
