Darshan Hadadi

Software Engineer

Bengaluru, Karnataka, India6 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in silicon design and performance validation.
  • Proven track record in debugging complex micro-architectural issues.
  • Strong background in VLSI and embedded systems.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in performance validation and debugging.

Contact

LinkedIn

Skills

Core Skills

Silicon DesignPerformance ValidationCore Design VerificationMicro-architecture

Other Skills

Micro-benchmarksDebuggingMicro-architecture ToolTraffic AggregatorRoot-causing RTL/DV IssuesBranch Predictor FeaturesC (Programming Language)VerilogEmbedded CAssembly Language8051 MicrocontrollerInternet of Things (IoT)x86 AssemblyX86Very-Large-Scale Integration (VLSI)

Experience

6 yrs 8 mos
Total Experience
3 yrs 4 mos
Average Tenure
3 yrs 10 mos
Current Experience

Tenstorrent

3 roles

Staff Engineer, Cores

Nov 2025 – Present · 6 mos

Sr. CPU DV Engineer

Promoted

May 2024 – Present · 2 yrs

CPU DV Engineer

Jun 2022 – Apr 2024 · 1 yr 10 mos

Amd

2 roles

Silicon Design Engineer 2

Promoted

Jul 2021 – Jun 2022 · 11 mos

  • Worked on Zen5 high performance core in performance validation team.
  • Role includes validating performance benefit of new feature added in Core by writing directed tests. Was responsible for validating new features added in Core blocks like OpCache, L2 Cache performance by writing targeted micro-benchmarks.
  • Contributed to development of micro-arch tool that aids in debugging complex fails at Core level. Worked on L3/fabric level traffic aggregator which is crucial for extracting performance metrics.
Performance ValidationMicro-benchmarksDebuggingMicro-architecture ToolTraffic AggregatorSilicon Design

Contractor - Core Design Verification

Jul 2019 – Jun 2021 · 1 yr 11 mos

  • Started my carrier with AMD working in Core team, worked on Zen4 high performance x86 core.
  • Debugging micro-architectural fails at Core level, root-causing RTL/DV issues.
  • Contributed to bringup of advanced branch predictor features in front-end block verification.
DebuggingRoot-causing RTL/DV IssuesBranch Predictor FeaturesCore Design VerificationMicro-architecture

Whizchip design technologies pvt ltd

VLSI Design Engineer

Jun 2019 – Jul 2019 · 1 mo · Bengaluru Area, India

Education

Bapuji Institute of Engineering & Technology, DAVANAGERE

Bachelor of Engineering - BE

Jan 2015 – Jan 2019

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