Gayathri R

Product Manager

Bengaluru, Karnataka, India10 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI and Physical Design
Experience with leading EDA tools and methodologies
Strong background in hardware description languages

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and FPGA technologies.

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Skills

Core Skills

VlsiPhysical DesignLayout VerificationBlock Level Implementation

Other Skills

PerlVerilogMatlabFPGACTCLUnixWindowsASICStatic Timing AnalysisICCCadence VirtuosoPlace & RouteEDAModelSim

About

Seeking a challenging positon in the field of VLSI design/Physical Design Currently working in INTEL as a Graphics Hardware Engineer (Contractor) Completed Internship in INTEL . Completed Mtech in VLSI Design from VIT University, Vellore ,Tamil Nadu EDA Tools : Synopsys ICC Complier. Cadence Virtuoso Hardware Description Languages : Verliog Scripting Languages : Perl , Tcl Software Languages : C , Matlab Design Tool : ModelSim FPGA Synthesis Tools : Xilinx ISE , Altera Quartus II Device Modelling and Simulation : Silvaco Interested Field : ASIC Physical Design and Scripting

Experience

10 yrs 11 mos

Total Experience

5 yrs 5 mos

Average Tenure

9 yrs 6 mos

Current Experience

Cadence design systems

Prinipal Application Engineer

Dec 2016 – Present · 9 yrs 6 mos · Bengaluru, Karnataka, India

PerlVerilogMatlabFPGACTCL+15

Intel corporation

2 roles

Graphics Hardware Engineer

Jan 2016 – Sep 2016 · 8 mos · Bangalore

Working on Partition from Synthesis till GDSII Flow
Layout Verification:
Have done Layout Verification for few blocks including DRC , LVS Correction . Fixing DFM , Antenna Voilations and helped in moving the Partitions for Tapeout

Layout VerificationDRCLVS CorrectionDFMAntenna ViolationsGDSII Flow+1

Intern

Oct 2014 – Jul 2015 · 9 mos · bangalore

Block Level implementation (APR complete Flow) in 22nm technology node for three different blocks of different levels of complexity.
Scaling down the same blocks to 14nm by scaling the Macros size, Core size, Pin size to a ratio for the best timing results and congestion free design.
ILMs are extracted for all the three blocks in 22nm and 14nm for the hierarchical level implementation.

Block Level ImplementationAPR Complete Flow22nm Technology Node14nm ScalingILMs ExtractionVLSI