Hiran Palothpoyil

Software Engineer

Bengaluru, Karnataka, India15 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI and Physical Design methodologies.
  • Proficient in using Synopsys and Cadence tools.
  • Strong background in low-power design and timing closure.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Physical Design.

Contact

LinkedIn

Skills

Core Skills

VlsiPhysical Design

Other Skills

Place & RouteLogic SynthesisFloorplanningClock Tree SynthesisStatic Timing AnalysisLow-power DesignTiming ClosurePhysical VerificationDRCLayout Versus Schematic (LVS)Signal IntegrityCMOSShell ScriptingTCLAwk

Experience

15 yrs 8 mos
Total Experience
7 yrs 10 mos
Average Tenure
12 yrs 9 mos
Current Experience

Amd

4 roles

SMTS Silicon Design Engineer

Promoted

Jul 2024 – Present · 1 yr 10 mos

VLSIPhysical DesignPlace & RouteLogic SynthesisFloorplanningClock Tree Synthesis+18

Member Of Technical Staff

Jul 2020 – Jul 2024 · 4 yrs

CaliberShell ScriptingLow-power DesignLogic SynthesisVLSIPhysical Verification+17

Sr. Design Engineer

Promoted

Jan 2016 – Jul 2020 · 4 yrs 6 mos

CaliberShell ScriptingLow-power DesignLogic SynthesisVLSIPhysical Verification+17

Design Engineer 2

Jul 2013 – Dec 2015 · 2 yrs 5 mos

CaliberShell ScriptingCadence EncounterLow-power DesignLogic SynthesisVLSI+18

Wipro technologies

Project Engineer

Aug 2010 – Jul 2013 · 2 yrs 11 mos · Cochin Area, India

  • ASIC Physical Design : IO placing, Floor planning, Power route, Analog route, Physical verification, Design rule violations analysis, Metal ECO works, Timing correlation experiments, Synthesis, Netlist functional ECO implementation.
  • Hands on experience and expertise in both Cadence and Synopsys tools.
CaliberShell ScriptingLogic SynthesisVLSIPhysical VerificationPhysical Design+9

Education

College of Engineering Trivandrum

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2006 – Jan 2010

Ramavilasam Higher Secondary School, Chokli, Thalassery, Kannur

11th to 12th Standard

Jan 2003 – Jan 2005

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