Jaya Anand Suhaas Vegi — Product Engineer
I am a VLSI Design & Verification Engineer with practical experience in RTL verification, SystemVerilog/UVM, and Formal Verification (FRV/FPV). At Synopsys, I work on verifying high-speed interfaces like MIPI CD-PHY, contributing to RTL & GLS simulations, coverage closure, formal checks, and debugging using VCS, Verdi, and VC Formal. At Maven Silicon, I gained hands-on experience working on real-time verification environments, strengthening my foundation in Digital Design, Verilog RTL, and UVM-based testbench development. I contributed to building a complete UVM testbench for AXI VIP, developing driver and monitor components, writing assertions, and implementing functional coverage to validate AXI protocol behavior. I bring strong analytical and debugging skills, a structured verification approach, and experience building reliable verification environments that ensure design correctness through both dynamic and formal methods. I am actively seeking opportunities in Design Verification and Formal Verification, where I can add value by improving design correctness, coverage quality, and overall silicon reliability.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI design and formal verification methodologies.
Location: Hyderabad, Telangana, India
Experience: 4 mos
Skills
- Functional Verification
- Formal Verification
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in VLSI Design and Verification methodologies.
- Proficient in SystemVerilog and UVM for testbench development.
- Strong analytical skills with a focus on design correctness.
Work Experience
HCLTech
IP Verification Engineer @ AMD (4 mos)
Synopsys Inc
IP Design Verification Intern (1 yr 1 mo)
GeeksforGeeks
Technical Content Writer (3 mos)
Maven Silicon
Advanced Design and Verification Trainee (7 mos)
Remotasks
Freelance (1 mo)
GirlScript Summer of Code
Open-Source Contributor (5 mos)
The 10x Academy
DSA Mentor (3 mos)
return_0
Social Media Manager (2 yrs 11 mos)
E-Cell, IIIT Dharwad
Web Developer (1 yr 3 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Information Technology Dharwad
12th at FIITJEE
10th at Aditya Public School - India
