Jaya Tripathi

Software Engineer

Bengaluru, Karnataka, India9 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8+ years in ASIC/SoC design expertise
Proven track record in timing closure
Strong collaboration with cross-functional teams

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on Static Timing Analysis.

Contact

Skills

Core Skills

Static Timing AnalysisAsic/soc Design

Other Skills

Synopsys PrimetimeClockingCONSTRAINTSFULL-CHIP & BLOCK LEVEL STATIMING ECOlow-power analysismulti-mode multi-corner (MMMC) analysisClock Tree SynthesisVerilogMatlabResearchTanner ToolsH-SpiceUnixSpeech Signal Processing

About

Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in static timing analysis, convergence and sign-off. Strong engineering professional with a Master of Technology (M.Tech.) focused in VLSI from ABV-Indian Institute of Information Technology and Management.

Experience

9 yrs 5 mos

Total Experience

4 yrs 8 mos

Average Tenure

8 yrs 10 mos

Current Experience

Intel corporation

Senior Static Timing Analysis (STA) Engineer

Aug 2017 – Present · 8 yrs 10 mos · Bengaluru, Karnataka, India

Senior Static Timing Analysis Engineer with 8+ years of experience in ASIC/SoC design, specializing in full-chip and block-level timing closure across advanced technology nodes . Proven expertise in constraint development, timing ECOs, signoff STA, low-power analysis, and cross-functional collaboration with PD, synthesis, and DFT teams. Strong background in PrimeTime, multi-mode multi-corner (MMMC) analysis, and delivering timing-clean silicon for high-performance designs.

Synopsys PrimetimeClockingCONSTRAINTSFULL-CHIP & BLOCK LEVEL STATIMING ECOlow-power analysis+3