S

Sunil Kumar

Director of Engineering

Bengaluru, Karnataka, India32 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Successfully taped out over 6 chips.
  • Expert in high-speed design for processors and SoC.
  • Rich experience in timing closure and physical design.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignTiming ClosureSynthesisLogic DesignVerification

Other Skills

RTL to GATESGDSHigh speed processor implementationRoutingClock tree synthesisVerilog codingPost silicon verificationASIC/SOC designRTL model writingPhysical synthesisValidationSoCProcessorsVerilogPrimetime

About

. My experience incldues High speed design for processors, SOC design viz wireless chips. Successfully tapedout more than 6 chips. Working on 65nm and beyond technology. Convereged designs for timing goals of 4GHZ and above Rich experience in routing ASTRO/ENCOUNTER, noise analysis, IR drop , Synthesis( DC/ICC), APR flow based on synopsys tools, timing analysis using primetime and PTSI. Specialties: VERILOG SYNTHESIS ( DC FLOW constraints generation) APR flow ( placement using ICC/PC and routing through ASTRO) Timing closure using CAD tools

Experience

32 yrs 4 mos
Total Experience
6 yrs 9 mos
Average Tenure
21 yrs 7 mos
Current Experience

Intel india ltd

2 roles

Engineering Manager

Promoted

Jan 2010 – Present · 16 yrs 4 mos

  • Doing Physical design basically converting RTL to GATES and physical design till GDS for tapeout.
Physical designRTL to GATESGDSTiming ClosurePhysical Design

Sr design engineer

Oct 2004 – Dec 2009 · 5 yrs 2 mos

  • Physical design, High speed processor implementation in Backend design. Doing Synthesis, routing, clock tress synthesis, and leading a team of people to accomplish task,
Physical designHigh speed processor implementationSynthesisRoutingClock tree synthesisPhysical Design

Amd

design engineer

Oct 2001 – Oct 2004 · 3 yrs

  • Synthesis of design
  • logic design / routing / timing closure of design
SynthesisLogic designRoutingTiming closureLogic DesignTiming Closure

Freescale

MTS

Aug 1999 – Oct 2001 · 2 yrs 2 mos

  • Verification of module level design using verilog
  • Writing codes in verilog for the design
  • Post silicon verification of the chip.
  • Synthesis of the module using Design compiler.
  • Lead a team of engineers to accomplish the tasks.
VerificationVerilog codingPost silicon verificationSynthesis

Motorola

MTS

Jan 1999 – Jan 2001 · 2 yrs

  • Verification of ASIC/SOC design
  • BLOCK level verification
  • Fullchip verification
  • RTL model writing in Verilog for Intel Memory
  • Team lead managing a team of 6 people
  • Physical synthesis / DC for the design.
VerificationASIC/SOC designRTL model writingPhysical synthesisPhysical Design

Vlsi software ltd

MTS

Jan 1999 – Jan 1999 · 0 mo

  • Verilog coding for processor. Validation using cycle accurate methodolgy
Verilog codingValidation

Altos india ltd

Design Lead

Jan 1993 – Jan 1998 · 5 yrs

Education

College of Engg

Btech — Electronics

Kendriya Vidyalaya

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