Sep 2023 – Aug 2024 · 11 mos

• 3nm FloorPlan, PNR & Block level Timing Closer, IR Sing-off Closer. Details : 1 Block, Gate Count 0.9M, Macro Count : 78, FT Count: 2.5K, Ports: 1.5K Challenges :
• Actively Working with Cadence and Design team to converge timing at Place stage.
• Techniques like Path groups and Pre-placement to achieve better timing Optimization.
• Executing multiple Floor Plans to Achieve Better core area and timing optimization.
• Leakage optimization and meeting timing at block level.
• Cleaning up FT cross talk & clock trans reported from SOC timing.

Dec 2022 – Aug 2023 · 8 mos

• 3nm FloorPlan, PNR & Block level, Timing Closer, IR Sing-off Closer. Details : 1 Block, Gate Count 2.3M, Macro Count : 113, Ports: 6.4K Challenges
• To Achieve better ID numbers, Done the pre-placement in clock path and did the multiple CTS trails.
• Timing Closer and DRV cleanup in Turbo corner was Challenging.
• Executed multiple Floor Plans to Achieve Better area reduction and timing optimization and achieved the 65% utilization at Floorplan stage.
• Responsible for Timing Closure, Running DMSA, Tweaker Eco Generation for block level setup timing violations.
• Manually cleaning congestion in ECO Phase.
• Manually Adding M1 shunts in critical areas to clean Dynamic IR.

Mar 2022 – Nov 2022 · 8 mos

• 5nm FloorPlan & PNR. Details : 1 Block, Gate Count 2.3M, Macro Count : 173, Ports 6K Challenges :
• Solving missing Lef & Lib issues at FloorPlan Stage.
• Very Challenging FloorPlan with More than 150+ Macros.
• Meeting SOC timing Paths, Done the Pipeline Pre-Placement.
• Meeting the DFT requirements by pre-placeing OCC logic.

Jul 2021 – Feb 2022 · 7 mos

• 3nm FloorPlan & PNR. Details : 1 Block, Gate Count 3M, Macro Count : 260, Ports 5K Challenges :
• Solving missing Lef & link issues at Floorplan and PNR Stage
• Executing Multiple FloorPlan to achieve better timing & core area.
• Solving the congestion Due to Sub-Hm Sharpe edges & high port density.