Kamal Vaishnav

CEO

Noida, Uttar Pradesh, India5 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in ASIC verification processes.
  • Proficient in Shell Scripting and Verilog.
  • Lead Design Engineer with strong project management skills.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogVerilog

Other Skills

Application-Specific Integrated Circuits (ASIC)BashDebuggingEcc_ScrubbingError Injection InterfaceFunctional CoverageGDDR6Organization SkillsRegression TestingRegular ExpressionsShell ScriptingSimphy Behavioral ModelSubversionTest Planning

About

At Cadence Design Systems, our team leverages my expertise in Shell Scripting and Verilog to enhance ASIC verification processes, an area where I've excelled since my time at eInfochips. With a solid educational foundation from Poornima Institute of Engineering & Technology in Electrical, Electronics, and Communications Engineering, I have quickly ascended to a Lead Design Engineer role. My proficiency with SV,UVM and a Linux bash Shell scripting certification from Udemy underpin my technical competencies, enabling me to contribute effectively to our design engineering projects.

Experience

5 yrs 5 mos
Total Experience
2 yrs 8 mos
Average Tenure
3 yrs 6 mos
Current Experience

Cadence design systems

2 roles

Lead Design verification Engineer

Jul 2024Present · 1 yr 11 mos · Noida, Uttar Pradesh, India · On-site

Universal Verification Methodology (UVM)SystemVerilogVerilogShell Scripting

Design Verification Engineer II

Dec 2022Jul 2024 · 1 yr 7 mos · Noida, Uttar Pradesh, India · On-site

  • GDDR6 BG disable Implemented support for Bank Group Disable in GDDR6, ensuring the functionality of both Bank group enable and Disable, and contributing to the overall improvement of the product. Created comprehensive coverage for the implemented feature, facilitating full Functional and Code coverage closure and ensuring the robustness and reliability of the design. Collaborated with cross-functional teams to identify and resolve issues, ensuring the seamless integration of the new feature into the existing system. Maintained clear and concise documentation, providing valuable insights and instructions for future reference and knowledge transfer. Ecc_Scrubbing Ecc_Scrubbing is a controller feature in which controller issue dummy reads and ecc mechanism of controller helped in correcting the errors if encnounterd. Added support for Pause to one of the scrub mechanisms in Ecc_Scrubbing, enhancing the functionality and effectiveness of the controller feature. Developed a comprehensive verification plan and successfully drove the project to completion, including functional coverage analysis. Ran regression to fully proof the design changes from error and to make the existing design broken free. Simphy Behavioral Model Update A Phy is used to communicate between dram and controller . The testbench uses a behavioural model of the same . Updated the Simphy Model to support front door initialization and Mode register Writes. Before the update initialization and mode register were done via back-door using the Tb . After the update Simphy was responsible to do MRW from front- door during initialization and frequency change operation.
GDDR6Functional CoverageEcc_ScrubbingSimphy Behavioral ModelSystemVerilogVerilog

Einfochips (an arrow company)

ASIC verification Engineer

Jan 2021Dec 2022 · 1 yr 11 mos · Ahmedabad, Gujarat, India

  • Developed an error injection interface for various signals of HBM3 Memory, significantly enhancing the controller's error detection and correction capabilities.
  • Created and optimized scripts for regression testing and coverage file generation, ensuring thorough testing and comprehensive analysis of the verification environment.
  • Successfully debugged IP and VIP failures, identifying and resolving issues to maintain the integrity and functionality of the verification process.
Error Injection InterfaceRegression TestingDebuggingVerilog

Iiht ltd

Cloud Architect

May 2019Jul 2019 · 2 mos · Jaipur, Rajasthan, India

  • I worked as a cloud architect.I choose the AWS cloud platform because of its popularity among the industries.

Defence research and development laboratory (drdl) - drdo

Internship Trainee

Jun 2018Jul 2018 · 1 mo · Delhi, India

  • I was introduced to vast field of HEMT(high electron mobility transistor) .why it is better then other silicon devices such as BJT ,FET and CMOS and what are its applications

Education

Poornima Institute of Engineering & Technology jaipur

Bachelor of Technology - BTech

Jan 2016Jan 2020

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