Kamal Vaishnav — CEO
At Cadence Design Systems, our team leverages my expertise in Shell Scripting and Verilog to enhance ASIC verification processes, an area where I've excelled since my time at eInfochips. With a solid educational foundation from Poornima Institute of Engineering & Technology in Electrical, Electronics, and Communications Engineering, I have quickly ascended to a Lead Design Engineer role. My proficiency with SV,UVM and a Linux bash Shell scripting certification from Udemy underpin my technical competencies, enabling me to contribute effectively to our design engineering projects.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.
Location: Noida, Uttar Pradesh, India
Experience: 5 yrs 5 mos
Skills
- Universal Verification Methodology (uvm)
- Systemverilog
- Verilog
Career Highlights
- Expertise in ASIC verification processes.
- Proficient in Shell Scripting and Verilog.
- Lead Design Engineer with strong project management skills.
Work Experience
Cadence Design Systems
Lead Design verification Engineer (1 yr 11 mos)
Design Verification Engineer II (1 yr 7 mos)
eInfochips (An Arrow Company)
ASIC verification Engineer (1 yr 11 mos)
IIHT Ltd
Cloud Architect (2 mos)
Defence Research and Development Laboratory (DRDL) - DRDO
Internship Trainee (1 mo)
Education
Bachelor of Technology - BTech at Poornima Institute of Engineering & Technology jaipur