Karthik S

DevOps Engineer

Bengaluru, Karnataka, India8 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in analog and mixed-signal circuit design.
Designed critical circuits for ISRO's ADC biasing.
Gold medalist with a strong academic background.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog and digital circuit design.

Contact

Skills

Core Skills

Static Timing AnalysisDebuggingAnalog Circuit Design

Other Skills

Timing ClosurePrimetime ToolCurrent Reference Circuit DesignField-Programmable Gate Arrays (FPGA)Circuit DesignRF DesignAnalog CircuitsDigital VLSI Circuits DesignVirtuosoCadence VirtuosoInnovusGenus

About

My research Interests are towards analog circuit design, mixed signals, RF IC design and Digital circuit design. I have designed process, voltage and temperature compensated current reference circuit for biasing the ADC for ISRO. Have worked on various projects across digital, analog, RF designs, FPGA and processor architecture as well.

Experience

8 yrs 3 mos

Total Experience

2 yrs 9 mos

Average Tenure

5 yrs 11 mos

Current Experience

Qualcomm

4 roles

Senior Lead Engineer

Nov 2024 – Present · 1 yr 6 mos

Senior Engineer

Promoted

Nov 2022 – Nov 2024 · 2 yrs

STA Engineer

Jun 2020 – Nov 2022 · 2 yrs 5 mos

I currently work in QCT PD signoff team of Qualcomm, where I debug setup and hold failures and give fixes for them, report and give ECO's for TDRC, voltage mappings for entire SOC, timing closure for SOC with 200+ robust corners.

Static Timing AnalysisDebuggingTiming Closure

Interim Engineering Intern

Jan 2020 – Jun 2020 · 5 mos

Working as intern in QCT PD Signoff - BDC team of Qualcomm india. I am working on Static timing analysis at SOC level and block level for various projects using primetime tool.

Static Timing AnalysisPrimetime Tool

International institute of information technology bangalore

Teaching Assistant

Aug 2019 – Jan 2020 · 5 mos · Bengaluru Area, India

Teaching assistant for computer architecture course for iMtech 2nd year students.

Isro - indian space research organization

Research Engineer

Jan 2019 – Nov 2019 · 10 mos · Banglore

Designed an ideal current reference which is process independent, temperature independent and supply variation independent. This reference circuit will be used to bias analog to digital converter. Reference current was designed in 180nm SCL PDK. This project was done at IIIT Banglore under guidance of Prof Dr. Chetan Parikh and Prof Dr. Subajit Sen

Analog Circuit DesignCurrent Reference Circuit Design