Jan 2025 – Mar 2026 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

• Start-up to build high performance, low-cost AI server with both external and in-house Silicon and Server hardware. I am leading package (2.5D) design and development effort integrating multiple chiplets and HBMs, aligning Server hardware architecture and topology for scale-up and scale-out.

Nov 2014 – May 2025 · 10 yrs 6 mos · Bangalore · On-site

• As System-In-Package Architect / Concept Engineer, IC-Pkg-PCB Co-design,
• Specialize in package system level optimization by applying innovative co-design methodology.
• Working on challenging mixed-signal SiP for Wireless Modem/Wearable/IOTG leading end to end Package Concept-Architect / PKG development / Co-design while applying Platform aware package strategy achieving best miniaturization. Also helping in Platform/SoC power analysis and debug.
• Key responsibilities:
• Driving complete package development for Modem/Wearable product, focussed on
• Small form-factor Package concept / architect in sync with platform need
• IC-Package-PCB System Co-design , IO Ring/ Bump planning, and Package substrate design
• Signal & Power Integrity analysis, SSN/SSO, High Speed Serial interface Analysis
• Drive Package System Thermal analysis
• Contribution to platform concept engg, IO muxing, Pad selection
• Closely working with SoC Architecture/implementation team to achieve best power delivery in package platform, also help in post Silicon Power measurement analysis , debug and optimization.

May 2011 – Nov 2014 · 3 yrs 6 mos · Bangalore

• Leading IC-Packaging CoDesign team, responsible for new products package development for mobile market
• Experience with package selection, stack-up definition, feasibility analysis and design with wirebond, flipchip, stacked die
• Die and board level co-design – pad ordering / IO ring design, bump planning, package interconnects, ball assignment and board alignment
• Defining package and board level routing guidelines for critical interfaces (DDR, PCIe, LLI, digRF, USB)
• Signal Integrity and Power Integrity modeling for package and board
• Methodology definition for high speed interface closure and compliance checks for packages and boards
• Electrical modeling of package/board, extracting signal+power nets, defining & performing simulations
• Interface with cross-functional groups throughout the package development phase, close working with system/architecture team, with focus on power optimization
• Coming from ST-Ericsson, I also worked as Physical Design Team Lead for SoC Integration and SoC IPs Physical Design activity.

Jan 2008 – May 2011 · 3 yrs 4 mos · Bangalore India

• Lead for testchip activity on advance technology nodes, silicon debug for digital libraries (StdCell/Memories)
• Technical leadership for overall backend flow of RTL2GDS including synthesis/P&R/STA/power analysis with Synopsys based flow (DC/ICC/PT/prime-rail) along with physical verification
• Responsible for delivering custom modules used for measuring library performance in advance node of 32/40/65nm
• Drive a lot of automation/scripting on the P&R backend/PT for routine verification of timing for high precision design blocks used for silicon qualification of memories.
• Responsible for Deep Sub-micron (DSM) Effect analysis & Design Sign-Off activity primarily for Digital flow involving Timing / Leakage / Cross-Talk etc. Created innovative methods to analyze to silicon measured for OCV.
• Supported on larger SOC backend activity for Wireline/Wireless products for STA/Physical verification

Aug 2004 – Apr 2006 · 1 yr 8 mos · Bangalore, India

• Responsible for Analog Simulation flow/methodologies for Infineon AMS flow, well versed with Cadence Virtuoso/Skill.
• Also worked for Advance Statistical methodologies to analysis variation in circuit performance due to DSM effects

Apr 2006 – Jan 2008 · 1 yr 9 mos

• Started Product Engineering team in India for Magma (acquired by Synopsys) new Custom Design Business Unit, focusing to develop industry next generation full custom design platform, TITAN.
• This tool was targeted for Full custom IC design, in competition to Candace Virtuoso platform, and we developed it from scratch.

Dec 1999 – Jul 2004 · 4 yrs 7 mos

• In Cadence Design System, I have been associated with R&D-PV activity, for various product divisions including PCB/ Analog circuit simulation and Full-custom IC design tools.
• Worked on the Cadence products development for CeltIC accuracy correlation with Spectre simulator and Spice Analog Simulators and Advance Analysis Platform including BSIM transistor modeling and verification
• Completed M Tech in VLSI design from IIT-Delhi (sponsored by cadence)

Jan 1997 – Jan 1999 · 2 yrs

• I worked for Camera Electronics subsystem Design for Remote Sensing Satellite application, image sensor subsystem for Ocean imagery . I build my strong Analog/Mixed-Signal knowledge while working for various Analog circuits designs like voltage regulators, digitizer involving ADC/DAC, OP-Amp based amplifier at PCB domain.