Kartik Kalia

CEO

Delhi, India6 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in Physical Synthesis and Static Timing Analysis.
Proficient in Perl automation and Synopsys tools.
Strong leadership in managing complex design projects.

Stackforce AI infers this person is a Digital Design Engineer with expertise in semiconductor design and automation.

Contact

Skills

Core Skills

Physical SynthesisSynopsys Design CompilerStatic Timing AnalysisSynthesis

Other Skills

3nm nodeFront End SynthesisSynopsys toolsECO flowPerl scriptingSQLProduct management fundamentalsOperations ManagementOrganizational BehaviorFinancial AccountingManagement AccountingEnglishPresentationsPerformance MetricsPresentation Skills

About

Experienced Digital Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Perl automation and usage of Synopsys tools for ex: Primetime and Design Compiler. Strong engineering professional with a Bachelor of Technology (B.Tech.) focused in Electronics and communications engineering from Netaji Subhas Institute of Technology.

Experience

6 yrs 8 mos

Total Experience

6 yrs

Average Tenure

8 mos

Current Experience

Siliconus technologies pvt ltd

Technical Lead

Oct 2025 – Present · 8 mos · Remote

Leading the physical implementation of multiple partitions.
Responsible for Physical Synthesis on 3nm node.

Physical Synthesis3nm nodeSynopsys Design Compiler

Amazon

Pathways Intern

Jul 2025 – Sep 2025 · 2 mos · Romford, England, United Kingdom · On-site

Stmicroelectronics

3 roles

Technical Lead

Promoted

Apr 2022 – Jul 2024 · 2 yrs 3 mos

Leading Front End Synthesis team for QoR closure on multiple designs.
Reference for various Front-End Synthesis and STA activities.
Responsible for Physical Synthesis on 5nm TSMC FINFET libraries.
Performing Static Timing Analysis and timing closure on macros and top-level designs.
Creating clock tree synthesis and placement guidelines for macros and top-level designs.
Executing 5nm TSMC Signoff STA Flow guidelines.
Developing Multi mode constraints and running constraint validation checks on macros and top-level designs.
Responsible for executing lint, LEC, and other Sign-off custom checks on macros and top-level design.
Successfully executed numerous successful ECO flows for timing closure and design change.
Expert in PERL, TCL, and Unix scripting and automation.
Central manager of all the Sign-off STA kits.
Experienced in Synopsys tools such as Primetime, Fusion Compiler, Design Compiler, Formality, Tweaker, Excellicon

Front End SynthesisStatic Timing AnalysisPhysical SynthesisSynopsys tools

Senior Digital Design Engineer

Nov 2020 – Apr 2022 · 1 yr 5 mos

Responsible for Physical Synthesis on 7nm TSMC FINFET libraries.
Performing Static Timing Analysis and timing closure on macros and top-level designs.
Creating clock tree synthesis and placement guidelines for macros and top-level designs.
Executing 7nm TSMC Signoff STA Flow guidelines.
Developing Multi mode constraints and running constraint validation checks on macros and top-level designs.
Responsible for executing lint, LEC, and other Signoff custom checks on macros and top-level design.
Executed numerous successful ECO flows for timing closure and design change.
Expert in PERL, TCL, and Unix scripting and automation.
Central manager of all the Signoff STA kits.
Experienced in Synopsys tools such as Primetime, Design Compiler, Formality, Tweaker, Excellicon

Physical SynthesisStatic Timing AnalysisSynopsys tools

Digital Design Engineer

Jul 2018 – Nov 2020 · 2 yrs 4 mos

Responsible for Synthesis and Static Timing Analysis on 7nm FINFET designs. Executing full RTL to GDS flow, Signoff STA, Multi mode constraints and Executing ECO flow.
Responsible for PERL, TCL and unix scripting and automation

SynthesisStatic Timing AnalysisECO flow