Lalit singh

Software Engineer

Bengaluru, Karnataka, India11 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in 5G algorithms and ASIC design.
Proficient in RTL design and verification methodologies.
Strong background in hardware prototyping and software architecture.

Stackforce AI infers this person is a 5G and ASIC design expert with a strong focus on hardware engineering.

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Skills

Core Skills

Asic Ip/soc Design5g TechnologyAsic Rtl DesignVlsi DesignFpga DesignHardware Engineering

Other Skills

5G NR algorithms5G New Radio (NR)AMBA AHBAPBARM ArchitectureASIC IP/SOC design flowsAXIAltera QuartusAnalytical SkillsApplication-Specific Integrated Circuits (ASIC)AssertionAssertion Based VerificationCC++CDC

About

* Developed 5G algorithms on ASIC platform using Verilog/VHDL/SystemVerilog * Designed 5G PDSCH receiver using Catapult HLS in C++ * Strong knowledge of 5G NR protocol and 3GPP 38.211 specification * Experienced in ASIC IP/SOC design flows, including timing closure and CDC * Proficient in writing SV/UVM testbenches for 5G sub-IP and SoC level verification * Authored micro-architecture for compute subsystem and clock controller * Defined timing and design constraints for compute subsystem from scratch * Involved in RTL design, lint checks, CDC analysis, and UPF generation * Collaborated with system architects to finalize IP design specifications * Supported software team in HW prototyping and SW architecture definition for next-gen IPs * High performer, self-driven, and experienced in MODEM/WLAN IP Design

Experience

11 yrs 8 mos

Total Experience

2 yrs 6 mos

Average Tenure

1 yr 6 mos

Current Experience

Arm

Staff Design Engineer

Dec 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

Understanding of compute subsystems mucro-architecture.
Developed timing and design constraints for compute subsystem from scratch.
Micro-architecture of clock controller cpuss

ASIC IP/SOC design flowstiming closureCDCmicro-architecturedesign constraintsASIC IP/SOC design+1

Qualcomm

Senior ASIC RTL Design Engineer

May 2021 – Dec 2024 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Worked on different MODEM IP Design.
Microarch of the specs, RTL Design, Lint check, CDC check and UPF generation.
Closely worked with the architecture team to define and finalize the design specs of the assigned IP.
Helped the software team in HW prototyping to define SW architecture to develop the architecture for next gen IPs

MODEM IP DesignRTL DesignLint checkCDC checkUPF generationASIC RTL Design+1

Nokia

5G L1 VLSI Design Engineer

Jul 2018 – May 2021 · 2 yrs 10 mos · Bengaluru, Karnataka

Reponsible to develope 5G NR algorithms in RTL as well as High Level Synthesis CATAPULT.
worked on L1_LOW RTL Design including CP removal, FFT, Guard band removal. Also experience in developing C++ design with HLS catapult
Worked on generating test bench in SV/UVM and verifying design.

5G NR algorithmsHigh Level SynthesisRTL DesignSV/UVMC++5G technology+1

Ministry of defence of india

Hardware Engineer

Jun 2016 – Jul 2018 · 2 yrs 1 mo · New Delhi

1To design complete FPGA project .
2.To develope and reuse IPs given by Xilinx Core .
3.Successfully developed MIL-1553B receiver and transmitter IP in FPGA and implemented BC-RT , RT-RT, RT-BC communication.
4. Successfully implemented RADAR Signal Simulator in FPGA only by using HDL (Verilog/VHDL) done all floating and fixed point mathematics successful ly by reusing Xilinx core gen IP and developing own UART IP.

FPGA project designIP developmentVerilog/VHDLfloating and fixed point mathematicsFPGA DesignHardware Engineering

Pine training academy

Trainee

Sep 2014 – May 2016 · 1 yr 8 mos · Govindpram,ghaziabad

1.I did industrial level training in PINE training academy.
2. I have learned there about VHDL/Verilog and DSP at system generator and advance level Digital design practice.

VHDLVerilogDSPDigital design