Manish Agarwal

DevOps Engineer

Bengaluru, Karnataka, India20 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Functional Verification and SystemVerilog.
  • Led multiple teams in complex networking projects.
  • Strong background in low-power design methodologies.
Stackforce AI infers this person is a Verification Engineer specializing in Networking and SoC design.

Contact

Skills

Core Skills

SystemverilogFunctional VerificationUniversal Verification Methodology (uvm)Open Verification MethodologyMemory Management

Other Skills

PCIPCIeTSNSoCVerilogASICVHDLRTL designStatic Timing AnalysisEthernetNetworkingVirtualizationDFTAMBAJoint Test Action Group (JTAG)

Experience

20 yrs 8 mos
Total Experience
2 yrs 7 mos
Average Tenure
3 yrs
Current Experience

Amd

Senior Member of Technical Staff

May 2023Present · 3 yrs · Bangalore Urban, Karnataka, India · Hybrid

Open Verification MethodologyPCIPCIeTSNUniversal Verification Methodology (UVM)SoC+15

Intel corporation

2 roles

Verification Team Lead

Promoted

Aug 2017May 2023 · 5 yrs 9 mos · Bengaluru Area, India · Hybrid

  • Multi Gigabit Ethernet TSN Subsystem :
  • => Leading verification team to develop a scalable UVM based PCI multi-function verif environment
  • => Test plan development,
  • => Defining test bench architecture and test strategy for all features.
  • => Quality execution from team which requires thorough code reviews, Debugs, waveform reviews etc.
  • => In addition to verification efforts, significant efforts were made to refine the architecture definition.
  • Open vSwitch IP :
  • => Lead Pre-Si verification team to develop a UVM based verif environment to verify OVS design.
  • => The design supports packet classifier, Tunnel packet decap/encap, FIB lookup, traffic policing, Ingress rate limiting, Egress Traffic Shaper, IP fragmentation, Metering etc.
  • => Test plan development,
  • => Defining test bench architecture and test strategy for all features and quality execution from team
NetworkingAMBALow-power DesignTSNEthernetUniversal Verification Methodology (UVM)+2

Sr Verification Engineer

Aug 2011Jun 2017 · 5 yrs 10 mos · Bengaluru, Karnataka, India · On-site

  • IOSF to OCP/AMBA Bridge IP verification :
  • Verification of SoC specific target configurations.
  • UPF based low power verification along with clock gating, multiple PCI functions, MSI, MSIX, PCI capabilities, Cold/warm reset flows, FLR, etc are some of the major features verified.
  • Mobile NoC IP verification :
  • Lead verification efforts for development of generic OVM based environment to be able to verify multi-master/slave configurations of different IOSF/AMBA/IFL/OCP bridges
AMBAPCIPCIeOpen Verification MethodologySystemVerilogFunctional Verification

Arm embedded technologies pvt ltd

Sr Verification Engineer (Consultant)

May 2010Aug 2011 · 1 yr 3 mos · Bangalore · On-site

  • System MMU Verification:
  • Create the test bench setup for the Translation Control Unit (TCU).
  • Test development and debug for all bypass modes, all 3 levels of page table walks, prefetch buffer, walk caches, global and context fault scenarios, TLB debug feature
  • Modeling of TLB debug feature and bug fixes in model
  • Functional cover points determination, coding and analysis.
  • Driver development: Translation Buffer Unit (TBU), APB3/4
  • Bus functional model (BFM) development: TBU, Page table walk
Memory ManagementSystemVerilog

Montalvo systems

Verification Engineer (Consultant)

Aug 2007Mar 2008 · 7 mos · Bangalore

  • Verification of Test Logic in SoC

Blueberry chip design services pvt. ltd

Design Verification Engineer

Mar 2007May 2010 · 3 yrs 2 mos · Bengaluru Area, India · On-site

  • IP Verification using System Verilog
AMBASystemVerilog

Laxmi remote india pvt ltd

Senior Application Engineer

Oct 2005Jul 2006 · 9 mos · Noida · On-site

  • Responsible for prototype development for AC remote control solutions

Abacus softech ltd

Tech Support Engineer

Jul 2004Jun 2005 · 11 mos · New Delhi Area, India · On-site

  • Involved into the development of Smart Card based Access Control System

Education

CDAC, Mumbai

PG Diploma — VLSI Design

Jan 2006Jan 2007

IEC College of Engineering and Technology

B.Tech — Electronics and Communication

Jan 2000Jan 2004

TRM Public School

Intermediate

Jan 1985Jan 1999

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Manish Agarwal - DevOps Engineer | Stackforce