Muzaffar Ameerali — Software Engineer
Worked on : Floorplanning. Placement, Congestion analysis and fixing, CTS, MMMC, Routing, Extraction, SI analysis. Low Power Methodologies. Power planning and Power analysis (EM, IR analysis and Fixes). Timing closure, Timing sign off , ECO implementation. Physical Verification : DRC , LVS analysis and fixes. Tools Experience: Placement and Routing : IC - Compiler I, IC - Compiler II, SOC Encounter, Magma Talus STA : Primetime LEC : Conformal Physical verification : Calibre Scripting : Perl, TCL, UNIX Shell
Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in ASIC development.
Location: Bengaluru, Karnataka, India
Experience: 14 yrs 9 mos
Skills
- Physical Design
- Vlsi
Career Highlights
- Expert in VLSI and Physical Design methodologies.
- Proficient in timing closure and power analysis.
- Extensive experience with industry-standard tools.
Work Experience
MediaTek
Senior Staff Engineer (4 yrs 11 mos)
Staff Engineer (3 yrs 10 mos)
Wipro
Technical Lead (1 yr)
Senior Project Engineer (2 yrs)
Project Engineer (3 yrs)
Education
B Tech at College of Engineering Trivandrum
Plus Two at Kendriya Vidyalay No.2,Kasaragod
Xth at Sa-adiya English Medium School,Kasaragod