Piyush Shriwastava — Software Engineer
• Hands on Experience in System Verilog, Verilog & VHDL. • Good Knowledge of UVM (Universal Verification Methodology). • Good understanding of SoC level Test bench Architecture • Good understanding of Verification flow at SoC level • Good Knowledge of FPGA, ASIC & SoC Design & Verification Life Cycles. • Excellent understanding of protocols like UART,SPI,I2C & AXI • Expertise in System Verilog UVM/OVM/VMM based ASIC Design Verification on assertion based Constrained Random Verification (CRV) with Functional and Code coverage and RTL (Verilog HDL & VHDL) development • Good Knowledge in functional verification • Familiar with basic concepts of C, C++ and Object Oriented Methodology. • Technical support to team members • Sound Knowledge of PERL
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in ASIC and FPGA technologies.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 10 mos
Career Highlights
- Expertise in System Verilog UVM-based ASIC Design Verification.
- Strong understanding of SoC level verification architecture.
- Hands-on experience with multiple hardware description languages.
Work Experience
AMD
Member of Technical Staff (1 yr 11 mos)
Senior Design Engineer (4 yrs 2 mos)
Intel Corporation
Design Engineer (7 mos)
L&T Technology Services
Senior Member Of Technical Staff (3 yrs 2 mos)
CETPA Infotech Pvt. ltd.
VLSI Engineer (3 yrs)
Education
Bachelor of Technology - BTech at Dr. A.P.J. Abdul Kalam Technical University
