Sep 2023 – Jan 2026 · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

• Heading a pre-silicon verification group for functional verification and FPGA validation of the best class IP's/Subsystem for camera image signal processing and Display for flagship Galaxy Mobile Products
• Screening the profiles in hiring the right talent in forming the verification group from scratch
• Lead to build the automation of simulation scripts, test bench template standardization and regression management for functional verification of IP's/Subsystem.
• Manage & Mentor the team for technical difficulties for successful execution of the projects.
• Hands-on contribution for testplan, execution plan process and development of UVM verification infrastructure from scratch for IP/Subsystem of ISP's and display.
• Strong contributor, Reviewer and Lead for checklist items process in-order to achieve the verification milestone criteria for zero silicon bugs.
• Leading and managing the FPGA validation infra and quality deliverables for all camera and display IP's

Sep 2019 – Sep 2023 · 4 yrs

• Implement testplan, UVM testbench Architecture planning from Scratch, managed and lead the team with setting up verification milestones besides working as individual contributor and tape out checklist signoff.
• Working experience on integration of all third-party VIP’s and verify I2C, UART, SSI (SPI’s+ QSPI),
• CAN-FD, I2S, SDIO, GPIO, DMA, USB, SOC IO system functionality, VISA (debug), FuSa features and Int
• Controller blocks.
• Core member of post silicon bring up for PMU, CCU, IO system and managed support for all SOC blocks.
• Managing and lead SOC activities for DDR, ATM/ATE, GLS & few top-level flows.
• Worked closely with architects & designers in delivering the verification with high quality.

May 2018 – Aug 2019 · 1 yr 3 mos

• Verification of Power management controller in Graphics Processor
•  Verified power licence flows, security and fuse store features
•  Implementation of test plan, assertion based self-checking mechanism, functional and code
• coverage closure.
•  Formal property verification (FPV) for identified units to perform formal verification

Oct 2015 – Apr 2018 · 2 yrs 6 mos · San Jose, California, United States

• Touch and Display Controller System Verification (Team Lead)
•  Created test plan , implemented system level tests and verified the full system
•  Verified One Time Programmable (OTP) controller and system security.
•  Responsible for test plan and verification of MBIST controller
•  Implemented assertion based coverage to verify the touch and display interface
•  Developed system Verilog test case from test bench environment into the intermittent
• playback tool readable format to perform playback simulations.
•  Core team member of Chip Bring up support

Oct 2014 – Sep 2015 · 11 mos · San Jose, California, United States

•  Gate-level simulation bring up and debug the tests
•  Worked on RAL model and integrated into the UVM environment
•  Flash memory Controller UVM block level development and Verification

Feb 2012 – Sep 2014 · 2 yrs 7 mos · San Jose, California, United States

• Touch digital system verification
• Full chip level test bench development and integration
• Verified I2C, SPI, NVM flash controller, system security and touch analog controller Transmitter/Receiver(TRX) blocks
• Verified the system debugger and test interfaces
• Gate-level simulation bring up and debug the tests
• I2C block level UVM environment development with interrupt mechanism
• Developed the UVM template structure
• Worked on RAL model and integrated into the UVM environment

Jul 2010 – Jan 2012 · 1 yr 6 mos · Bangalore

• Consultant@ Qualcomm, Bangalore, India (July’10 – Jan’12)
• Verification of Cache Controller (04/11 - 01/12)
•  Test plan development for implementing cover groups.
•  Developed coverage model environment in OVM environment.
•  Worked on functional coverage and code coverage closure.
• Verification of MIPI- Slimbus Slave (07/10 - 03/11)
•  Integrated and verified Nsys-AHB interface.
•  Developed test cases using OVM methodology on messaging part
•  Developed functional coverage exclusion file using Vmanager.

Aug 2009 – Jul 2010 · 11 mos · Noida Area, India

• Given training SV,OVM in Mentor Graphics for HEP which is being conducted by Masamb Electronics and Mentor Graphics.
• Consultant@Freescale Semiconductor, Noida, India
• SOC level Verification of DSP chip (Nov’09 – July’10)
•  Developed system level verification plan document for GPIO and GIC (Global Interrupt
• Controller) and AD -tagging
•  Developed test cases in Verilog to verify both system level functionality and integration.
• Consultant@ STMicroelectronics, Noida, India
• Automation of Verification environment and integrating VIP’s (Aug’09 – Oct’09)
•  Developed Scripts for running regression tests using Perl
•  Integration of OVM VIPs for developing regression Environments
•  Integration of SystemC environment with e for getting Functional Coverage.
•  Created and Integrated in Vplan.

Oct 2008 – May 2009 · 7 mos · Hyderabad Area, India

• Verification of Processor Core Instruction Set Architecture (ISA)
•  Developed Functional Accurate Model.
•  Developed test cases in Assembly for four groups of Instructions-Arithmetic Instructions,
• Custom Instructions, Floating Point Instructions and Control Instructions.
•  Participated in development of Self-checking Verification Environment and Functional Coverage.

Feb 2007 – Sep 2008 · 1 yr 7 mos · Hyderabad Area, India

• Trained in SystemVerilog, e-language and OVM
• Development of OCP- eVC and OVC (03/08 - 09/08)
• Development of AMBA 3 APB – eVC and UVC (12/07 - 02/08)
• SPI eVC & UVC development (08/07 - 11/07)
•  Test plan, protocol checkers and functional Coverage
•  OVC & eVC env with OVM & eRM compliance respectively.

Jul 2006 – Jan 2007 · 6 mos

• Got Cadence EDA tools Experience for Full Custom ASIC Design while doing VLSI design Training in VEDANT, Chandigarh certified by Semiconductor Complex Ltd under Cadence University Program