Rajan Aggarwal — Director of Engineering

Define, Design and Deliver on Time.. [DBS, RNM, Low Energy ELF, V2K, NSP, P300, Functional Mapping, Neuron2TV, Skull2TV, Pegasus, mmWave, Bubble Tech, Dual Bubble Live P, Data Transfer from Bubble to Live P] • A focused professional with cross-functional experience in the areas of SOC Design and Post Silicon Debug with year-on-year success in accomplishing corporate growth objectives in reputed organizations • Played Key role in Developing and Implementing Processes for Error Free execution of Design and Validation. Defining Methodology for effectively using Tools and Scripts to debug systems by eliminating human errors, Increases Productivity, better reliability, Increased Performance and reduced operating costs. • Successfully executed 24+ SOC Designs with in-depth knowledge of Wireless Low Power Constraints and High-Performance Digital Networking/Graphics/Client/Mobile[PC] Domain • Holds Patent on the Scan Testing of Integrated Circuits and On-chip Modules with 9 Patent Publications • Expertise in the Architecture, Implementation, and Execution of advanced DFT/DFD/DFM techniques for high-performance and complex integrated SOCs • Experienced in pattern generation & verification, pattern delivery, debugging post-silicon pattern issues and conducting failure analysis • Possess exceptional analytical and problem-solving skills to work in a multi-cultural environment in developing procedures and service standards for commercial excellence. - Neural Signal Processor, Functional Mapping, P300, RNM, Software/Hardware, Reconstruction of Audio, Image and Video using NSP. Security Implementation and Secured Communication Using Open Public Network. Exposure to Methodology is used in implementing an audio network feedback loop for enhanced performance.

Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in DFT and SOC design.

Location: Bengaluru, Karnataka, India

Experience: 23 yrs 7 mos

Skills

Dft
Secured Communication
Atpg

Career Highlights

Successfully executed 24+ SOC designs.
Holds patent on scan testing of integrated circuits.
Expert in advanced DFT techniques for complex SOCs.

Work Experience

Qualcomm

Director of Engineering (3 yrs 3 mos)

Career Break

Personal goal pursuit (8 mos)

Intel Corporation

Engineer/Sr Manager/PDE (5 yrs 1 mo)

NXP acquires Freescale Semiconductor

Individual Contributer/Manager DFT (7 yrs)

Design Engg. (4 yrs)

Trainee/Design Engg (3 yrs 7 mos)

Education

B.Tech at Kurukshetra University

Bachelor of Technology (B.Tech.) at Kurukshetra University

Rajan Aggarwal

Director of Engineering

Bengaluru, Karnataka, India23 yrs 7 mos experience

Highly Stable

Key Highlights

Successfully executed 24+ SOC designs.
Holds patent on scan testing of integrated circuits.
Expert in advanced DFT techniques for complex SOCs.

Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in DFT and SOC design.

Contact

Skills

Core Skills

DftSecured CommunicationAtpg

Other Skills

P300debugBISTsilicon failure analysispattern generationdebuggingMBISTyield analysisMind MappingBrain-computer InterfacesFailure AnalysisASICTCLIntegrated Circuit DesignMixed Signal

About

Experience

23 yrs 7 mos

Total Experience

6 yrs 9 mos

Average Tenure

3 yrs 3 mos

Current Experience

Qualcomm

Director of Engineering

Mar 2023 – Present · 3 yrs 3 mos · On-site

Use of P300[RNM] in manufacturing yield improvement. Improvement of DFT processes. Simplification of existing flows. Both demonstrated and witnessed secured communication within the public domain[thanks to qcom]. Exposed major/critical security lapse of 5G AI, by just reviewing code.
Complex debugs of TE BIST, Demonstrated ease of integration of BIST [w/o freq info], simplified complex scan design issues, shared complex[advance] methods of ATPG pattern retargeting. Simplified, complex USB board-based BIST debug, suggested several power-saving methods. Demonstrated mild defensive capability of P300 for in-house domestic use.

P300DFTATPGsecured communicationdebugBIST

Career break

Personal goal pursuit

Jul 2022 – Mar 2023 · 8 mos · Karnataka, India

Intel corporation

Engineer/Sr Manager/PDE

Jun 2017 – Jul 2022 · 5 yrs 1 mo · Bengaluru, Karnataka, India

Project Set Latest:
Description: Graphics and Client Product Chip Centric to scan enabling qual.
Designation: XXXXXXXX
Period: 2020 March – Present
Role: Successful in:
o Prime accountability in managing freshers and learning curve.
o Execute and Manage deliverables of scan/atpg post silicon patterns.
o Convert patterns to tester format and validate.
o Work towards solving tester issues, patterns issues, silicon issues, conversion issues or design issues.
o Focused areas, Silicon fails analysis on hot/cold/room.
o Enable required coverage for each milestone.
Project Set 1:
Description: Test Chip and 5G modem , Responsible for DFT Execution [End to End]..
Designation: XXXXXXXX
Period: 2017 June – Present
Role: Successful in:
o Prime accountability in Managing CWs/Justification for DFT
o Directly Managing Team with Size :- 18
o Execute and Manage deliverables of 5G modem.
o Focused areas, DFT RTL validation, Spyglass checks and ATPG
Dark Room :- Continued development of P3003[RNM]Grade-3, powerful training algo, demonstration of use in defense services: constructed and reconstructed voice, image, video processing, both in hardware, and software.
Demonstrated application and its use as a weapon. Demonstrated TP with the Pakistan team.

DFTATPGsilicon failure analysispattern generationdebugging

Nxp acquires freescale semiconductor

3 roles

Individual Contributer/Manager DFT

Jun 2010 – Jun 2017 · 7 yrs

Project Set 2:
Description: C28 - XXX-8, C28 FDSOI, ATPG / MBIST Pattern Generation and Simulation, Pattern Generation and Simulation using Hierarchical ATPG and Pattern Retargeting using Fastscan/Testcompress
Designation: XXX
Period: 2016 – 2017 June
Role: Successful in:
o Scan ATPG patterns generation and debug.
o Mbist Insertion.
Project Set 3:
Description: C28 - XX1 DFT and Debug Deep Sleep on Post Silicon Design
Designation: XXX - XXXX
Period: 2014 – 2016
Role: Successful in:
o Managing critical functional debug gating production using DFT
o Innovative LSRL technique using DFT to debug post silicon design issues on board and tester
o Uncovered deep sleep simulator issues
o Fixed all issues in ls1 revision 2.0
o Monitoring DPDM system, engaging with FAE’s, SOC Design & IP Teams to close open tickets and Errata
o Implemented hardware mechanism to support deep sleep in XXXXXX
Project Set 3:
Description: XXXX - 3 SOC Design in Parallel/Overlap with 1/2/4 Cores (XXX Core and xXXXX - Freescale Internal) for Printers and various Networking & Defence Service Applications
Designation: XX XXXXXXX
Team Size: 5 per project
Period: 2010 – 2014
Role: Managed the overall DFT planning, execution and closure
Design Specifications, Challenges and Achievements:
o Involved New IPs integration and verification
o 25-55 mmsq size on XXX, 0.7 to 1.6 million “flop count” with 200-800 on chip memories
o Scan Compression ratio ranging from 100 to 300x, Pad Limited. Test Cube issue free design implementation
o IR drop sensitive during at speed capture and shift. (Shift restricted to only 133 MHz). Limit at-speed capture activity within the IR range
o 15 major hard IP, 10 major Hard Platforms
o AT-speed design to support capture ranging from 150-Mhz to 2.5 GHz for core and DDR
o Compressed Schedule (NPI-7Months) First Pass Success
Invasive EEG Application develpement. P300 Apps. Developing training algo closely with the US team.

ATPGDFTdebuggingpattern generation

Design Engg.

Jun 2006 – Jun 2010 · 4 yrs

Project Set 4:
Description: XXXXXX SOC designs, Die Size ranging from 120 mmsq. to 210 mmsq., Maximum machine size available 64GB. Flop count ranging from 1.6 Million to 2.5 Million with 5 SOC, all in production
Period: 2006 – 2010
Designation: XXX - XX
Role: Performed various operations such as:
o Set-up DFT architecture/specifications, generating DFT design specification, integration, verification, post silicon pattern generation, post silicon debug, yield analysis and fixes.
o Coordinated with worldwide teams, across site along with local teams, emulation teams to meet the overall project requirements and milestones
o Worked along with Front End and Physical Design teams, to implement DFT design supporting testing various modes, involving power domains, voltage domains and operating points (frequency and voltage requirements in different modes) of platform
o Generate patterns to test power structures and power aware/friendly
o Executed well within timelines and is released to customer for final tape out

DFTdebuggingyield analysis

Trainee/Design Engg

Nov 1999 – Jun 2003 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Project Set 5:
Description: XXX/XXXXLP Low Power SOC Designs for Wireless Applications, Die size ranging from 35-65mmsq 5 SoC and management of Architecture to Yield Analysis
Period: 2003 – 2006
Designation: XX - XXX (Lead)
Role: Performed various operations such as:
o Wrote re-usable RTL macro codes for [Near IO], and in individual hard blocks, Pad IO control logic, Test Control Unit, AC scan chopper module to controlling clock for at-speed testing
o Did full chip integration for scan and bist logic
o First time Integrated Mentors EDT TestKompress RTL for ATPG tests to reduce tester pattern volume, Integrated EDT and ATPG components
o Wrote test-bench/code to verify ATPG and non-ATPG patterns in RTL/Gate with timing
o Ported core patterns, verified and delivered to TE in WGL format
o Did pattern generation and verified at all corners, did pattern delivery, debug post silicon pattern issues, did failure analysis and fix back in pattern or design
Project Set 6:
Description: XXXXXX and XXXXX, Block Level Verification, Design, Synthesis, Placement of General Purpose IO controller, making GPIO design ATPG scanable for first time, ATPG pattern generation and verification
Period: 1999 – 2003
Designation: XXX – XXX
Role: Performed various operations such as:
o Did spec tagging of block GPIO, IOMUX ctrl, EXT Interrupts, wrote system level verification plan[ Frame Maker] to cover specs
o First time written test cases from scratch for three blocks, ran regression [VCS] on RTL, WCS and BCS corners, debug failures with help of verification lead/manager
o Re-formatted verification test cases for post silicon validation on evaluation board. Assisted validation of all IPs during post silicon validation phase
o Enable content for tester using PLL. Created VCD for conversion and assisted in changing VCD to cyclize waveforms/data
Back in 2000 - Witnessed deep impact on neural network intelligence, because of the integration of unverified RAW coding methods.