Abhishek Ghosh

Director of Engineering

Bengaluru, Karnataka, India19 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

20+ patents approved for circuit design innovations.
Leadership role in developing future leaders in technology.
Expertise across diverse technology nodes from 400nm to 7nm.

Stackforce AI infers this person is a semiconductor design expert with extensive experience in engineering and project management.

Contact

Skills

Core Skills

Engineering DesignProject Management

Other Skills

Team ManagementCross-functional Team LeadershipCoachingProject EngineeringRelationship BuildingProject PlanningSoftware DocumentationResource ManagementSemiconductorsEDADebuggingSPICETransistorsReliabilityESD and LU

Experience

19 yrs 10 mos

Total Experience

6 yrs 7 mos

Average Tenure

11 yrs

Current Experience

Samsung electronics

Director ▪️ Enabler - People & Technology ▪️Foundation IP Development

Jun 2015 – Present · 11 yrs · Bengaluru, Karnataka, India · On-site

► Design & Development Portfolio - Std Cell Library, IO, eNVM, Process Monitoring Structures, DTCO
► Architecture definition, Feasibility Analyses, Design, Optimization, Characterization, Modeling, Layout
► On Chip Parametrics, Process Monitoring Structure Design: Yield Engineering, MHC
► Library Development for range of technology nodes - Bulk CMOS, FinFETs, FDSOI, GAA
► Technology Node Understanding and expertise ranging from 400nm to the most recent Samsung nodes 7nm, SF5, SF4, SF3, SF2, GAA.
► Library development towards diverse range of customers - HPC, AI, Mobile, Servers, IoT, Display Drivers, Automotive, Flash, Sensors etc. to name a few within Samsung. Foundry Library development to vast number of customers outside Samsung.
► Customer interface: requirement/specification gathering, alignments, support
► Specific custom cell development to meet particular PPA goals for customers
► Communication and Collaboration: Across Samsung sites - India, Korea, US, Europe. Regular interactions across sites on Library & Testchip developments, customers, vendors.
► Memory & Standard Cell Testchip Design
► Circuit Design; Robustness; Reliability
► Innovation: Circuits, Methodology Exploration & Productization
► PPA, Benchmarking
► Vendor Interaction
► CAD, Design Automation
► Device Analysis
► Team Building, Mentoring & Collaboration
► Project Management: Project Planning, Tracking, Prioritization, Resource allocation, Budgeting across Library and Testchip projects
► Strong Documentation
► 20+ patents approved for filing from the team on circuit design, novel topologies/structures providing PPA differentiation
► Leadership role in SSIR; also involved passionately in developing more leaders both on Technical and People management ladders
► Campus ambassador towards hiring exciting freshers across the country; personally involved in their college to work-life transition, conducting technology and business overviews, induction to the company
► Passionate L&D ambassador
► Fun!

Team ManagementProject ManagementEngineering DesignCross-functional Team LeadershipCoachingProject Engineering+39

Immensa semiconductors

Semiconductors Enthusiast ▪️ Technology Consultant ▪️ Founding Member

Feb 2013 – Jun 2015 · 2 yrs 4 mos · Bengaluru Area, India

► Foundation IP Design - Standard Cells, Memories
► CAD, Design Automation
► Start-ups
► Customer Interaction
► Learning and Sharing
► Fun

Texas instruments

2 roles

Lead Engineer ▪️ On Chip Parametrics ▪️ Reliability ▪️ Yield Engineering

Jul 2006 – Jan 2013 · 6 yrs 6 mos

► Technology lead in On-Chip Parametric Design and Development; leading a diverse team of TI-ers, contractors and interns.
► Central POC for all parametric activities in TI across business units.
► Consultant to design teams for optimum placement of parametric structures on chips to ensure technology entitlement and add Si debug capabilities on package/probe.
► Drove 28nm TI product Si-SPICE correlations using ODP infrastructure aiding yield improvements for 28nm driver products.
► Facilitator for ‘Failure Analysis’ and Si debugs of driver products using parametric data and structures
► Worked on defining architecture and road-map of On Chip Parametric module design in 20nm and below technologies with close collaboration with process teams to enable a robust 20nm ODP technology specifically with external fab partners.
► Focused on expansion of scope of on chip/die parametrics to maximize design and process entitlement
Design of adaptive voltage scaling (AVS) sensors as part of parametric structures
Measuring capacitance of thru-silicon via (TSV) unit cell on die to understand more into its behavior on Si
► Worked on support for analog components in deep sub-micron technologies – including capacitance & transistor mismatch etc.
► Close work with SoC teams to convert 'design critical timing paths' into 'parametric cells' to characterize them across process corners etc. - Si correlation tool
► Close work with Product Engineering teams to reduce test time with different test algorithms tested through systematic simulations.
► ESD CAD consultant to ESD CAD/design teams. Worked on design, implementation and productization of a novel Electro Static Discharge (ESD) and Latch Up (LU) reliability solution.
► Interaction with internal and external customers in seamless integration and usage of IP at SoC level.

Intern ▪️ Analog Circuit Design

Dec 2005 – Feb 2006 · 2 mos

Interned with Mixed Signal Group in TI, India - worked on the schematic design of a two stage amplifier circuit on 65 nm technology node
Key Learnings:
First stint of industry exposure
design planning with given constraints
schematic designing, circuit stability analysis, first cut simulations

Ministry of electronics & information technology

Project Trainee

Jun 2005 – Jul 2005 · 1 mo · New Delhi, Delhi, India

Worked under the guidance of Dr. Om Vikas, Senior Director, Ministry of Information Technology in the lab - Technology Development of Indian Languages (TDIL) on the topic - Internationalization of Domain Names in Indian Languages
A paper on the topic was selected in the IETE journal of research, Vol 51, No 5, September - October, 2005
http://www.iete.info/journal_of_ed/Dsp05.htm