Thirukumaran N

CEO

Bengaluru, Karnataka, India18 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

18+ years in SoC execution and design leadership
Expertise in DFT and manufacturing test for chip quality
Holder of 4 patents and 15+ published papers

Stackforce AI infers this person is a semiconductor design expert with a focus on high-performance SoCs.

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Skills

Core Skills

Soc Integration And Subsystem ArchitectureChip Lead / Front-end Design Ownership

Other Skills

Front-End DesignDVDFTIP evaluationIntegrationDebugOTP Controller DesignDesignTiming ConstraintsProject Planning and Schedule-Driven DeliverySenior Engineering Management and Mentoring

About

Chip Lead and Front-End Design Lead with 18+ years of experience driving end-to-end SoC execution - from requirements and micro-architecture through RTL integration, tape-out readiness, silicon bring-up and post-silicon support. Currently at Arm Embedded Technologies as Principal Engineer, leading micro-architecture definition of front-end design for next-generation Agentic AI SoCs and server-class compute SoCs. Prior career at Analog Devices as Senior Engineering Manager and Chip Co-Lead across high-performance DSP/processor SoCs (65nm to 16nm). Owned full chip-level planning and execution: IP evaluation, micro-architecture, RTL design, SoC integration, STA, physical design support, FPGA/prototyping support and silicon debug. Designed reusable IPs - AXI prefetch buffer, OTP controller, L2 controller and Link Port DDR - deployed across multiple product families. Deep additional expertise in DFT and manufacturing test - low-power scan/MBIST, ATPG - applied to strengthen chip quality across every program. Holder of 4 patents | 1 trade secret | 15+ published papers in ADI ITEC / GTC / ITD, SNUG conferences

Experience

18 yrs

Total Experience

9 yrs 2 mos

Average Tenure

18 yrs

Current Experience

Arm

Principal Engineer

Feb 2026 – Present · 4 mos

Analog devices

2 roles

Senior Engineering Manager

Promoted

Apr 2022 – Present · 4 yrs 2 mos

ADSP-SC595/8 - Dual SHARC + Arm Cortex-A55, TSMC 28HPC+ | Front-End Design, DV and DFT Lead /Chip Co-Lead | IP evaluation, power/area estimation, spec updates, design releases, constraint reviews, GLS/DV debug, ECO handling, performance and power analysis. Delivered in short time; BMW-MARS automotive design win.
ADSP-SC83x - SHARC-FX + Arm M33, 16nm TSMC | Front-End Design, DV and DFT Lead
Front-end design integration for next-gen SHARC-FX + Arm M33 SoC; DV strategy and work allocation; DFT scope including scan, MBIST, memory repair and boundary scan.
ADSP-SC59x / ADSP-2159x - Dual SHARC + Arm A5, TSMC 28HPC+ | Front-End Design Lead
Led front-end design enhancements: L2 controller, Link Port peripheral, DAI, AXI prefetch buffer and NIC400 migration; full integration, constraints, GLS/DV debug and ECOs.
ADSP-21560 / 21561 / 21564, 22GF | Front-End Design and OTP Lead
OTP controller design and integration on 22GF process (third-party IP + in-house controller); delivered working silicon with zero owned-area bugs.
ADSP-2156x - SHARC-FX + Arm M33, TSMC 28HPC+ | Front-End Design Lead
Smart processor assist / prefetch buffer design, memory and IP integration, SoC interconnect, timing constraints, Lint/CDC, synthesis, LEC and ECO flows.

Chip Lead / Front-End Design OwnershipSoC Integration and Subsystem Architecture

Engineering Manager

Jun 2008 – Nov 2024 · 16 yrs 5 mos

ADSP-SC57x - SHARC + Arm Cortex-A5, TSMC 40LP | Front-End Design Lead
OTP controller micro-architecture and RTL design (security focused), STA closure and ECO support; DFT add-on: low-power scan/MBIST, at-speed/path-delay testing and silicon debug.
ADSP-2147x / 2148x / 2146x, TSMC 65nm
Design integration, IP integration, ATPG, scan vector GLS, power analysis, LEC and silicon support.