Rakesh Kandula — Software Engineer

Featured as Intel India Top Innovator consistently for 2022-2025 https://www.linkedin.com/posts/intel-corporation_inventors-from-intel-india-activity-7156126038689779713-LRcH/?utm_source=share&utm_medium=member_desktop Rakesh Kandula's Patent Portfolio https://patents.justia.com/inventor/rakesh-kandula Filed 32 US-Patents in the areas of Architecture, Foveros, 3D IC , 2.5D, Die to Die testing architecture, timing constraint verification, Infield System Test, Telemetry, Debug, Silicon Life Cycle Management Having 19 years of experience in Structured Micro-architecture Development ,Hands on RTL Design implementation , Logic Synthesis, IP Power Management Micro architecture/Architecture, UPF Development of IP/Subsystems , Unit Level / Full Chip Logical Equivalence Checking, Stuck@ & @speed SCAN DFT on Subsystems/IPs , Clock Domain Crossing Analysis , Fool proof Setup Multi Cycle Path analysis in RTL simulations, Timing annotated , Unit Level , zero Delay Gate level simulations. Structured Miro-architecture development of multi million gate designs from scratch that involves PCIe TLP protocol. Hands-on RTL logic development of multimillion gate designs involving PCIe TLP , complex arbitration , routing , Switching . Logic Synthesis , Multicycle path validation in RTL sims and timing RTL fixes after analyzing the timing reports from Synopsys DC of multi million gate Subsystems /IPs. UPF Development from scratch for mutli voltage and multi Power domain design and closure of Power rules using static tools. In depth experience of developing RTL design for power management control blocks that follows specific power rail and reset sequence Handson Stuck @ coverage and @speed Scan coverage analysis for various Subsystems/IPs by writing atpg dofiles and testproc files from scratch. Handson RTL fixes for scan coverage improvement by improving controllability and obervabability and from scan coverage analysis. Unitl Level and full chip logic equivalence checks and functional gate level checks for graphics partitions. Clock domain cross analysis for Multimillion gate Subsystems/IP designs and signoff. Tools expertise: a) RTL SIMS : Synopsys VCS, Verdi b)Power aware Sims : Synopsys VCS, Verdi c) Clock domain cross analysis : Mentor graphics 0in , Quest CDC d) UPF power rules closure : Spyglass LP , Synopsys CheckMV design e) Stuck @ and @speed SCAN DFT : Synsopsys DFT Cmpiler & Mentor Graphics ATPG f)Customized RTL design dev to check Multicyclepath validity in RTL sims

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on VLSI and micro-architecture design.

Location: Bengaluru, Karnataka, India

Experience: 19 yrs 7 mos