R

Rakessh Sannapureddy

Software Engineer

Bengaluru, Karnataka, India4 yrs experience
Most Likely To Switch

Key Highlights

  • 3+ years in ASIC/IP verification.
  • Expert in SystemVerilog and UVM methodologies.
  • Proven track record in delivering high-quality ASICs.
Stackforce AI infers this person is a skilled ASIC Verification Engineer with expertise in digital design and functional verification.

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Skills

Core Skills

Functional VerificationAxiAmba Ahb

Other Skills

PerlVerilogUSB ProtocolDigital DesignsUniversal Verification Methodology (UVM)APBSystemVerilog

About

• Design Verification Engineer with 3+ years of experience in ASIC/IP verification • Proven expertise in developing and executing comprehensive verification environments for complex IP blocks (PMBus, I2C, I2S masters) using SystemVerilog and UVM methodologies • Proficient in SystemVerilog Assertions (SVA), constraint-based verification, and Object-Oriented Programming • Strong foundation in AMBA protocols (APB, AHB, AXI) and scripting languages (Python, Perl) • Demonstrated ability to achieve high Functional Coverage through effective test plan creation and execution • Successfully contributed to delivering high-quality ASICs by identifying and resolving design issues • Seeking a challenging role to leverage skills and contribute to a dynamic organization's growth

Experience

4 yrs
Total Experience
1 yr 4 mos
Average Tenure
1 yr 9 mos
Current Experience

Synopsys inc

ASIC Digital Design Sr Engineer

Sep 2024Present · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

Functional VerificationPerl

Quest global

Design Verification Engineer

May 2024Sep 2024 · 4 mos · Bengaluru, Karnataka, India

AXIAMBA AHB

Cientra (an iso 9001:2015 company)

Verification Engineer

Jun 2022May 2024 · 1 yr 11 mos · Bengaluru, Karnataka, India

Functional VerificationVerilog

Education

Jawaharlal Nehru Technological University Anantapur (JNTUA)

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2018Jan 2022

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