Ripan Bansal

Software Engineer

Noida, Uttar Pradesh, India15 yrs 7 mos experience

Highly Stable

Key Highlights

14+ years in SoC design and integration.
Expert in UVM and verification methodologies.
Proven track record in automotive applications.

Stackforce AI infers this person is a specialist in Automotive SoC design and verification.

Contact

Skills

Core Skills

UvmVerificationDebugRtl GenerationTestbench Development

Other Skills

EthernetTrace subsystemI2CSPIAPBMagillemTiming analysisVerification plan developmentToggle coverage analysisJTAGMCVerilogASICSystem verilogUniversal Verification Methodology (UVM)

About

14+ years experience in Design-Integration activities on SoCs for Automotive and Compute applications. Skilled in Verification/Integration of various Communication(Ethernet, DSPI- Deserial serial peripheral interface), Safety(Fault collection and correction unit, Self test control unit, RCCU etc ) and Debug (Nexus, Aurora , JTAGM, SWD etc) related IPs for Automotive SoCs. Also having experience in clock architecture of SoC. Knowledge of various bus protocols like AXI,AHB,APB, IPS etc Hands on Experience in System Verilog, verilog and C and developing VIPs in UVM for SoC. Exposure to analysis of CDC issues on SoC. Experience in debugging Gate level simulation. Tool used : NCSIM, VPLANNER, MAGILLEM, GENSYS, ICCR , VMANAGER

Experience

15 yrs 7 mos

Total Experience

10 yrs 2 mos

Average Tenure

5 yrs 5 mos

Current Experience

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Nov 2024 – Present · 1 yr 7 mos · Noida, Uttar Pradesh, India

Staff Engineer

Jan 2021 – Nov 2024 · 3 yrs 10 mos · Noida, Uttar Pradesh, India

SoC Integration Lead

Stmicroelectronics

4 roles

Staff Engineer

Jul 2017 – Jan 2021 · 3 yrs 6 mos

Developed UVM based Serial Wire Debug VIP
Integration of Various IPs Ethernet,FCCU, Debug and Trace subsystem, DSPI, Aurora-LINK/PHY etc
Verification of I2C/SPI to APB
Generation of top RTL using Magillem
Providing support to STA team in constraint development for Communication IPs

UVMEthernetDebugTrace subsystemI2CSPI+3

Technical Lead

Promoted

Sep 2014 – Jun 2017 · 2 yrs 9 mos

RTL generation for IOMUX/PADRING structure of SoC using tortoise assembler
RTL/GLS Verification of DSPI IP on SoC.
Timing analysis for DSPI IP.
Debug and trace subsystem verification on PowerPC based SoC.

RTL generationVerificationTiming analysis

Senior Design Engineer

Promoted

Aug 2012 – Aug 2014 · 2 yrs

Testbench development for ARM based SoC.
Verification plan development/modification for the IPs to verify
Verification of FCCU- Fault correction and collection unit , MEMU-Memory error management unit on SoC
Toggle coverage analysis.

Testbench developmentVerification plan developmentToggle coverage analysisVerification