Rohit Mahajan

Software Engineer

Bengaluru, Karnataka, India15 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in variable gain amplifier design for ultra-wideband systems.
  • Proficient in algorithm-architecture transformation for DCT.
  • Strong background in VLSI system design and operational amplifiers.
Stackforce AI infers this person is a VLSI design engineer with expertise in analog and digital signal processing.

Contact

Skills

Other Skills

Cadence VirtuosoVHDL

About

1) Title : Variable gain Amplifier (VGA) Description : A fully differential CMOS variable gain amplifier (VGA) has been designed for an ultra-wideband receiver. The gain of the VGA varies dB-linearly with respect to the control voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz throughout the gain range to cater to the requirements of the ultra-wideband system. DC offset cancellation has also been incorporated to minimize the input referred DC offset caused by systematic and random mismatches in the circuit. Compensation schemes to minimize the effects of temperature, supply and process variations have been included in the design. 2) Title : Antilog Amplifier Description : Log amplifier is used in compression of input signal in many application . Antilog amplifier is used to recover original signal. In this project antilog amplifier has worked for 6 decade of dynamic range along with 1% log conformity error. Antilog amplifier require design of Operational amplifier with very low offset voltage. Antilog amplifier requires temperature compensation to reduce effect of temperature variation. 3) Title : 64 point Discrete Cosine Transform(DCT) Description : DCT is widely use in Speech & Image data compression. Hence this should be fast. Thus, in this project, Algorithm-Architecture Transformation algorithm is used, which is based on symmetric property of the DCT kernel matrix. This decomposes algorithm will reduce the numbers of multiplications. Specialties: Languages : C, VHDL. Operating Systems : Windows XP, LINUX Packages : Cadence (Virtuoso ADE), Mentor Graphics (ELDO),MAGMA,Tanner SPICE, Quartus-II, Modelsim, Xilinx ISE, MATLAB

Experience

15 yrs 2 mos
Total Experience
7 yrs 3 mos
Average Tenure
9 mos
Current Experience

Sandisk

Principal Engineer - System Design Engineering

Sep 2025Present · 9 mos

Intel corporation

Board Design Engineer

Aug 2011Oct 2025 · 14 yrs 2 mos · Bengaluru Area, India

Semtronics micro systems

2 roles

AMS Design Engineer

Jun 2011Jul 2011 · 1 mo

Internship

Jan 2011May 2011 · 4 mos

Education

National Institute of Technology Warangal

M.Tech — VLSI SYSTEM DESIGN

Jan 2009Jan 2011

Pune Vidhyarthi Griha’s College of Enggering Technology,Pune

B.E. (Electronics & Tele-communication Engineering)

Jan 2004Jan 2008

Moolji Jaitha College, Jalgaon

H.S.C

Jan 2002Jan 2004

Raoasaheb Rupchand Vidyalaya, Jalgaon

S.S.C

Jan 2001Jan 2002

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