S Sahil Ahamed

Software Engineer

Hyderabad, Telangana, India3 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Expertise in ASIC verification and digital logic design.
Hands-on experience with UVM and VMM methodologies.
Proven track record in high-speed SERDES PHY RTL verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with strong ASIC design capabilities.

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Skills

Core Skills

Digital VerificationAsic Verification

Other Skills

Universal Verification Methodology (UVM)Digital logic designVCSVerdiFPVFRVVMMFirmware validationCore JavaNetBeansMSQLopampsPower ElectronicsMicrocontrollersElectric Motors

About

Currently contributing as a ASIC Digital Verification Intern at Synopsys Inc, specializing in ASIC verification with expertise in SystemVerilog and Universal Verification Methodology (UVM) and VMM with expertise in tools like VCS compiler,Verdi debug tool and also on Firmware validation and Coverage, Collaborating on verification tasks to support the development of robust and efficient VLSI architectures and IP configurations. Graduated as an Electronics, and Communications Engineer at Amrita Vishwa Vidyapeetham. Dedicated to leveraging domain expertise and technical skills to enhance contributions in the field of semiconductor design and verification.

Experience

3 mos

Total Experience

3 mos

Average Tenure

3 mos

Current Experience

Synopsys inc

2 roles

ASIC Digital Design Engineer

Mar 2026 – Present · 3 mos · Hyderabad

Universal Verification Methodology (UVM)Digital logic designDigital verificationASIC verification

ASIC digital design verification Intern

Dec 2024 – Mar 2026 · 1 yr 3 mos · Hyderabad

Verified high-speed SERDES PHY RTL designs for PCIe, USB, HDMI, Ethernet, and M-PHY protocols.
Enhanced and maintained UVM and VMM-based testbenches with custom testcases, monitors, scoreboards,
assertions, and code/functional coverage.
Performed functional, formal verification (FPV/FRV), and regression verification using Synopsys VCS, Synopsys
Verdi and VC formal.
Executed post-silicon and firmware validation for customer nodes including Intel, AMD, and Samsung.
Supported RTL sign-off across technology nodes: 3nm, 5nm, 6nm, and 18nm.

Universal Verification Methodology (UVM)ASIC verificationVCSVerdiFPVFRV+1