Sagar Latti — Software Engineer

Hands on experience in Netlist to GDSII ASIC physical design implementation and CMOS concepts. Hands on experience on 10nm 8nm 7nm 5nm 4nm technologies. Successfully Involved in several Metal Tape out closures. Experience in Floorplan, Power Planning, APR, Physical Verification. Experience in Timing Closure, Timing Optimization, Clock Balancing Techniques. Experience in Synopsys ICC2, Primetime, Cadence Innovus, Redhawk , Mentor Callibre. Good Knowledge of Static Timing Analysis. Good Understanding of Electromigration, Crosstalk, ESD, Noise and Antenna Effects. Experience in Low Power Design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC physical design and VLSI technologies.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 11 mos