Nov 2014 – Apr 2015 · 5 mos · Greater Bengaluru Area

• Verilog modelling of standard cells and verification flows. Skilled in scripting and automation.
• Standard cell library verilog models generation:-
• > Worked on flow for automatic creation of verilog models for standard cells based on golden verilog as reference and .libs for the timing / constraint sections.
• Automatic test pattern generation flow:-
• > In order to test standard cell verilog vs. Spice, created an automatic test pattern generation flow that provides 100% coverage vectors.
• > This includes 1, 0 and x conditions.
• > Comprehends all possible previous & next states for sequential elements.

Jul 2013 – Jun 2014 · 11 mos · Greater Noida

• Project - Functional Verification of Imaging IP's using SV - UVM.
• Responsibilities :-
• Developing verification plan which lists IP features extracted from the specification and writing tests to cover those features.
• Developing testbench, sequences, scoreboard and integrating different VIP’s to create verification environment for a particular IP.
• Regression testing and analyzing, for functional and code coverage sign off.