Sowmya V S, PMP®

Program Manager

Bengaluru, Karnataka, India22 yrs 6 mos experience
Highly Stable

Key Highlights

  • Over two decades in semiconductor project management.
  • Expert in Physical Design and Verification methodologies.
  • Proven track record in team leadership and innovation.
Stackforce AI infers this person is a semiconductor industry expert with strong project management and engineering capabilities.

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Skills

Core Skills

System On A Chip (soc)

Other Skills

DRCPhysical VerificationASICPhysical DesignLVSICCFloorplanningCMOSCadence VirtuosoDesign Rule Checking (DRC)Static Timing AnalysisLayout Versus Schematic (LVS)

About

Accomplished Engineering Mgmt. Professional - Project Management | Physical Design & Verification | Place & Route | Full Chip Verification | LV Methodology Development | Digital Layout As a Visionary Engineering Executive with over two decades of distinguished career, I have led and nurtured cross-functional teams, steering multiple concurrent projects in semiconductor companies. I am specialized in Physical Design & Verification, Place & Route, Full Chip Verification, LV Methodology Development and Digital Layout. My focus has been on orchestrating comprehensive engineering activities, refining methodologies, and presenting pivotal initiatives to CxOs. In my role as an Inspiring People Leader, I have cultivated teams from inception within a six-year span, chaired interview panels, and collaborated closely with HR to streamline recruitment processes,revitalized underperforming teams, elevating engineers' innovative prowess and fostering a culture of accountability and ownership, crucial for advancing business objectives. I instituted annual rewards and team recognitions, and meticulously managed OKRs across all experience levels, fostering continuous improvement. Recognized as a Valued Business Partner, I have exerted influence across individuals, organizations, and technologies, forging robust collaborations across diverse teams to ensure streamlined communication and successful project deliveries. Actively engaged with IP development teams, participated in design reviews, facilitated final LV signoff approvals, and provided comprehensive post-project retrospectives. Additionally, I oversaw contract employee engagements, meticulously calculating and allocating budgets aligned with project requirements.

Experience

22 yrs 6 mos
Total Experience
5 yrs 2 mos
Average Tenure
1 yr 8 mos
Current Experience

Qualcomm

Program Manager-staff

Sep 2024Present · 1 yr 8 mos · Bengaluru, Karnataka, India

Intel corporation

2 roles

Physical Design Engineer

May 2013Jan 2020 · 6 yrs 8 mos · Bangalore

System on a Chip (SoC)

Engineering Manager

Apr 2013Sep 2024 · 11 yrs 5 mos · Bangalore

System on a Chip (SoC)

Texas instruments

Sr. Layout Design Engineer

Sep 2011Apr 2013 · 1 yr 7 mos · Bangalore

Lsi

Mask Designer

Aug 2005Sep 2011 · 6 yrs 1 mo

Cypress semiconductors

Mask Designer

Oct 2003Jul 2005 · 1 yr 9 mos

Education

Manipal Academy of Higher Education

MS — Microelectronics

Jan 2006Jan 2011

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