Sai Mani Bharath Nuti

Software Engineer

Bengaluru, Karnataka, India9 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and PPA.
Led UFS implementation at Micron Technology.
Contributed to high-performance computing at Synopsys.

Stackforce AI infers this person is a Semiconductor expert with a focus on Physical Design and PPA.

Contact

Skills

Core Skills

Physical DesignPpa

Other Skills

Very-Large-Scale Integration (VLSI)TCLPython (Programming Language)VerilogApplication-Specific Integrated Circuits (ASIC)CCMOSStatic Timing AnalysisFormal VerificationSynopsys IC Compiler II

About

At Synopsys Inc, I contribute to the research and development of high-performance computing and interface IP technologies, focusing on implementation, enablement, PPA, and technology. Leveraging my expertise in physical design and PPA, I collaborate to drive innovation and excellence in hardware development. With a Master’s and Bachelor’s degree in Electronics and Communication Engineering from JNTU Kakinada, my academic foundation complements my professional journey. My work at Micron Technology included implementing UFS 3.1 and 4.0-related blocks, while prior roles at Qualcomm and Altran further honed my technical skills in physical design and subsystem-level handling for advanced technology nodes.

Experience

9 yrs 4 mos

Total Experience

2 yrs 10 mos

Average Tenure

3 yrs 1 mo

Current Experience

Synopsys inc

R& D staff Engineer

May 2023 – Present · 3 yrs 1 mo · Bengaluru, Karnataka, India · On-site

Implementation, Enablement, PPA, Technology of HPC, Interface IP

Very-Large-Scale Integration (VLSI)TCLPhysical DesignPPA

Micron technology

Senior Engineer

May 2021 – May 2023 · 2 yrs · Hyderabad, Telangana, India · On-site

Worked on Implementation of UFS 3.1 and UFS 4.0 related blocks and leading activity using Innovus and FC

Very-Large-Scale Integration (VLSI)TCLPhysical DesignPPA

Qualcomm

Senior Hardware Engineer

Feb 2017 – May 2021 · 4 yrs 3 mos · Bengaluru Area, India · On-site

Block Level, Sub system level PD HANDLING of ISP Processor blocks WITH 5 tapeouts in lower technolgy nodes

Very-Large-Scale Integration (VLSI)TCLPhysical Design

Altran

Junior Engineer

Feb 2017 – Mar 2019 · 2 yrs 1 mo · Bangalore · On-site

Consultant at qualcomm during tenure at altran

Very-Large-Scale Integration (VLSI)TCL

Education

JNTU K

Masters degree

JNTU KAKINADA

Bachelor’s Degree — ECE

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