Sandesh Y. — DevOps Engineer
At Synopsys Inc, we're pushing the boundaries of semiconductor technology through cutting-edge Design for Testability (DFT) practices. My educational background, a Master of Technology in VLSI and Embedded Systems from B.M.S. College of Engineering, underpins my contributions to the development of state-of-the-art DFT solutions. With a solid foundation in Logic BIST, DFT Compiler, and Scan Insertion, my role as a Senior R&D Engineer focuses on enhancing the reliability and performance of advanced chip designs. Our team's collaborative efforts are pivotal in pioneering DFT innovations that shape the future of chip design.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT methodologies.
Location: Bengaluru, Karnataka, India
Experience: 3 yrs 6 mos
Skills
- Dft
- Testmax
- Scan Insertion
- Logic Bist
Career Highlights
- Expert in Design for Testability (DFT) solutions.
- Strong background in Logic BIST and Scan Insertion.
- Contributed to advanced chip design reliability and performance.
Work Experience
Synopsys Inc
Staff Research Development Engineer (1 mo)
Senior Research And Development Engineer (2 yrs 2 mos)
R&D Engineer 2 (7 mos)
AMD
Silicon design engineer (8 mos)
Education
Master of Technology - MTech at B. M. S. College of Engineering
