Sanjay U — Software Engineer
Physical Verification Engineer Experienced Physical Verification Engineer with proven track record on TSMC advanced technology nodes (16nm, 12nm, 7nm), driving successful project outcomes. Key expertise: - Top-Level Physical Verification (PV) & PERC: Demonstrated capability handling rigorous checks for large reticle-size chips. - Tools Proficiency: Hands-on experience with industry-leading tools Innovus, Calibre, and ICV, driving efficient design closure and verification. - Experienced in bump planning, RDL routing, and IO placement
Stackforce AI infers this person is a Physical Verification Engineer specializing in advanced semiconductor technologies.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 6 mos
Skills
- Physical Verification
- Soc Design
Career Highlights
- Expert in Physical Verification for advanced technology nodes.
- Proficient in tools like Innovus, Calibre, and ICV.
- Strong background in bump planning and RDL routing.
Work Experience
Meta
Silicon Engineer (5 mos)
Rivos Inc.
SoC Design Engineer (7 mos)
Alphawave Semi
Engineer II - ASIC Design (1 yr 4 mos)
Engineer I - ASIC Design (11 mos)
OpenFive
ASIC ENGINEER (2 yrs 3 mos)
Education
Bachelor of Engineering - BE at J N N College of Engineering, SHIMOGA
