S

sanjeev kumar

Software Engineer

Bengaluru, Karnataka, India16 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Senior Design Engineer with extensive VLSI expertise.
  • Proficient in Cadence Virtuoso and Static Timing Analysis.
  • Strong background in Verilog and VHDL design.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on semiconductor technology.

Contact

Skills

Core Skills

VlsiStatic Timing Analysis

Other Skills

Cadence VirtuosoVerilogVHDL

Experience

16 yrs
Total Experience
8 yrs
Average Tenure
13 yrs
Current Experience

Intel corporation

Senior Design Engineer

May 2013Present · 13 yrs · Bengaluru Area, India

Cadence VirtuosoVLSIVerilogVHDLStatic Timing Analysis

St microelectronics

design engineer, memory

Jan 2010Jan 2013 · 3 yrs · Noida Area, India

Education

faridabad

Bachelor of Engineering (BEng)

Jan 2004Jan 2008

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