V

Vishwanath Bhat

Software Engineer

Bengaluru, Karnataka, India31 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Principal Engineer with extensive experience in Physical Design.
  • Expert in Timing Closure and Static Timing Analysis.
  • Strong background in SoC and ASIC design.
Stackforce AI infers this person is a semiconductor design expert with a focus on physical design and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Static Timing AnalysisTimingSoCASICVerilogVLSIProcessorsSemiconductorsPerlPrimetime

Experience

31 yrs 1 mo
Total Experience
4 yrs 7 mos
Average Tenure
11 yrs 4 mos
Current Experience

Mediatek

Principal Engineer

Dec 2014 – Present · 11 yrs 4 mos · Bangalore

Physical DesignTiming ClosureStatic Timing AnalysisTimingSoCASIC+6

Open silicon bangalore

Design Manager

Dec 2012 – Dec 2014 · 2 yrs · Open Silicon

Esencia technology india private ltd.

Technical Director

Aug 2011 – Nov 2012 · 1 yr 3 mos

Intel corporation

Senior Design Engineer

Feb 2005 – Sep 2011 · 6 yrs 7 mos

Ammocore technology

Product Specialist

Jan 2002 – Jan 2005 · 3 yrs

Infineon technologies

Senior Design Engineer

Jan 2001 – Jan 2002 · 1 yr

Larsen & toubro limited, mysore works

Project Leader

Jan 1993 – Jan 1999 · 6 yrs

Larsen & toubro (l & t)

Project Leader

Jan 1993 – Jan 1999 · 6 yrs

Education

San José State University

MS — Engineering

Jan 2005 – Jan 2008

UVCE

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