Sarthak Saxena — Product Engineer
Experienced MTS Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Verilog, SystemVerilog, and UVM. Expertise in VIP Development & IP Verification. Have exposure to subsystem and full-chip Verification. Strong knowledge of Memory protocols such as DDR3/4, LPDDR3/4, GDDR6, HBM2 and PCIe Gen5/6.
Stackforce AI infers this person is a semiconductor design engineer with expertise in verification and memory protocols.
Location: Hyderabad, Telangana, India
Experience: 9 yrs 2 mos
Career Highlights
- Expert in Verilog, SystemVerilog, and UVM.
- Strong knowledge of memory protocols including DDR3/4 and PCIe Gen5/6.
- Proven experience in VIP Development and IP Verification.
Work Experience
AMD
Member of Technical Staff (1 yr 8 mos)
Senior Design Engineer (3 yrs)
Truechip Solutions
Senior Design Engineer (1 yr 8 mos)
Design Engineer (2 yrs 6 mos)
Trainee (4 mos)
Siemens
Summer Intern (1 mo)
Education
Post Graduation Diploma in VLSI Design at CDAC ACTS PUNE
Bachelor of Technology (B.Tech.) at Jaypee Institute of Information Technology, Noida
High School at Ryan International School , Noida
