Kuldeep Singh — Software Engineer
I am passionate about the work I do, ASIC/FPGA driven artificial intelligence excites me. I work on the design, analysis, simulation and validation of RTL IPs. Have taken up projects from scratch which involved re-using/modifying existing IPs and writing new IPs/modules.
Stackforce AI infers this person is a highly skilled RTL Design Engineer specializing in ASIC/FPGA technologies.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs 6 mos
Skills
- Rtl Design
- Digital Circuit Design
Career Highlights
- Expert in ASIC/FPGA driven AI design.
- Proficient in RTL IP design and validation.
- Strong leadership and teamwork abilities.
Work Experience
Qualcomm
Staff RTL Design Engineer (2 mos)
Tejas Networks
Lead Engineer - RTL Design (3 yrs 9 mos)
Senior RTL design Engineer (2 yrs 8 mos)
RTL design Engineer (2 yrs 11 mos)
Education
Bachelor of Technology (B.Tech.) at Motilal Nehru National Institute Of Technology
12th at Bishop Conrad Senior Secondary School Bareilly
High School at Bishop Conrad Senior Secondary School Bareilly
