Shashi Ranjan Upadhyay — Software Engineer

From researching advanced VLSI architectures at DTU to signing off 3nm designs at MediaTek, my journey has been driven by a deep fascination with silicon complexity and advanced node challenges. As a Senior Engineer in the Synthesis & STA domain, I specialize in driving timing closure and delivering signoff-quality results at sub-5nm nodes. My work involves navigating complexities such as multi-voltage domains (MVDD) and on-chip variations (AOCV), ensuring robust and reliable timing across MCMM scenarios. I bring end-to-end ownership across the timing flow—spanning Pre-STA setup, Post-STA convergence, and final signoff validation. I have hands-on experience in resolving setup/hold violations, implementing timing ECOs at both block and full-chip levels, and executing power ECOs to optimize PPA. Key highlights: • Achieved STA timing signoff at 3nm node • Strong focus on timing closure under advanced node constraints • Expertise in MVDD handling • Timing & Power ECO implementation (block and top level) • Synthesized and optimized critical designs (~2M instance block) • Performed rigorous STA quality checks for signoff reliability I focus on bridging the gap between architectural intent and physical implementation, leveraging industry-standard tools like PrimeTime to deliver efficient, scalable, and high-quality silicon solutions. I am continuously driven to deepen my expertise in advanced timing methodologies, optimization techniques, and automation, aiming to contribute to next-generation high-performance SoC designs. please feel free to reach out to me at shashi.upadhyay916@gmail.com

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in advanced VLSI architectures and timing analysis.

Location: Greater Delhi, Delhi, India

Experience: 10 mos