Jul 2025 – Present · 10 mos · Bengaluru, Karnataka, India · On-site

• As a "Senior Engineer" in RTL Design team at MediaTek, I work on frontend RTL development for high-performance SoCs. My responsibilities include micro-architecture planning, RTL coding, and ensuring design quality through lint checks, CDC analysis, and formal cleanups. I contribute to low-power architecture strategies and take ownership of key IP blocks from development through integration. The role involves active collaboration across teams, writing synthesizable and PPA-optimized RTL, participating in design reviews, and continuously refining specs and debug flows to ensure robust and efficient design handoffs.

Jan 2025 – Jun 2025 · 5 mos · Bengaluru, Karnataka, India · On-site

• As a Chip Design Trainee at MediaTek, I was involved in multiple aspects of digital design flow. I started with RTL synthesis, netlist generation, and timing analysis, gaining hands-on exposure to STA tools and constraints management. Gradually, I transitioned toward frontend RTL design, contributing to simulation readiness, lint/CDC cleanup, and RTL quality checks. The experience provided me a strong foundation in both implementation and design, along with an understanding of cross-functional design handoffs and backend readiness.