Surendra Reddy Peddapalle — Senior Software Engineer
TECHNOLOGY SKILLS • EDA Tools: Lattice diamond,Xilinx ( Vivado , ISE) ,QUARTUS,Modelsim,Questasim • Xilinx FPGA’s : Spartan6,Virtex5 • HDL: VHDL,Verilog • Qsys IP Integration • Good knowledge in Digital logic Design. • Basics of System Verilog and UVM • OtherTools: Matlab,Simulink
Stackforce AI infers this person is a Digital Design Engineer specializing in FPGA and RTL development.
Location: Hyderabad, Telangana, India
Experience: 7 yrs 3 mos
Career Highlights
- Expert in FPGA design and digital logic.
- Proficient in multiple EDA tools and HDL languages.
- Strong background in RTL design and verification.
Work Experience
AMD
Sr software development Engineer (1 yr 4 mos)
Software Development Engineer 2 (2 yrs 1 mo)
Capgemini Engineering
RTL design Engineer (9 mos)
Mistral Solutions Pvt. Ltd
Design Engineer - Hardware Design(RTL & FPGA design) (1 yr 2 mos)
Unizen Technologies Pvt Ltd
Associate FPGA engineer (1 yr 11 mos)
Sandeepani- School of Embedded System Design
Design and Verification Trainee (7 mos)
Education
Bachelor of Technology - BTech at RGMCET nandyal
