Shiva Singh — Business Development Executive
As an Analog Mixed-Signal (AMS) Verification Engineer, I specialize in ensuring the accuracy and reliability of complex mixed-signal designs and systems. I have hands-on experience with industry-standard tools such as Cadence AMS Designer, Cadence Spectre, Mentor Questa ADMS and Mentor Questa Visualizer. I am proficient in Verilog, System Verilog and SVA & have experience with UVM. I have good understanding of analog circuit design concepts, including op-amps, transistors, and related building blocks. I have strong understanding of verification concepts of blocks including BGR, Voltage Regulators, ADCs, DACs and amplifiers. TOOLS & PROGRAMMING SKILLS: • Design Tools: Cadence Virtuoso • EDA Simulators: Cadence AMSD, Cadence XCELIUM, Analog Design Environment, SPECTRE, Questa ADMS • Languages: Verilog, System Verilog, SVA • Debugging: SimVision, ViVA, Questa Visualizer, EZwave, nwave, Unix, Vim & GVIM • Documentation: MS-Office
Stackforce AI infers this person is a Mixed-Signal Verification Engineer with expertise in Analog Circuit Design and Functional Verification.
Location: Noida, Uttar Pradesh, India
Experience: 3 yrs 7 mos
Skills
- Mixed Signal Verification
- Assertion Based Verification
- Functional Verification
Career Highlights
- Expert in Mixed-Signal Verification with industry-standard tools.
- Proficient in Verilog, System Verilog, and UVM methodologies.
- Strong understanding of analog circuit design concepts.
Work Experience
Cadence
Senior AE - AMS (1 yr 2 mos)
onsemi
Design Engineer II - AMS (3 mos)
Capgemini Engineering
Professional I - Engineer (1 yr 2 mos)
Associate II (1 yr 3 mos)
Education
M.tech - Master of Technology at Indian Institute of Information Technology, Design and Manufacturing, Jabalpur
BTech - Bachelor of Technology at Dr. A.P.J. Abdul Kalam Technical University
