S

Shyam Sai Prasad Dogga

Software Engineer

Bengaluru, Karnataka, India1 mo experience

Key Highlights

  • Expert in PCIe verification and functional safety.
  • Hands-on experience with advanced verification methodologies.
  • Strong foundation in VLSI and digital design.
Stackforce AI infers this person is a VLSI and semiconductor design specialist with a focus on verification and functional safety.

Contact

Skills

Core Skills

Pcie Protocol & VerificationFunctional Safety (asf)

Other Skills

VerilogSystemVerilogDigital Design & VerificationFunctional Coverage & DebuggingPCIeFunctional coverageVerisium ManagerDigital ElectronicsCDCLeadershipVivadoESP8266QuestaSimSTARTL Design

About

Design Engineer 1 at Cadence | PCIe Verification | Functional Safety (ASF) | VLSI & Digital Design Enthusiast I am an Electronics and Communication Engineer with a strong passion for VLSI design, verification, and high-speed interface technologies. Currently, I am working as a Design Engineer 1 at Cadence in the PCIe Verification team, contributing to Functional Safety feature development and verification, with a focus on Automotive Safety Features (ASF). My work involves PCIe protocol verification, ASF integration, error injection, event logging, debugging, and protocol compliance testing to ensure reliable and safety-compliant system functionality. I have hands-on experience working on PCIe verification environments and functional safety features for next-generation systems. My technical expertise includes: • PCIe Protocol & Verification • Functional Safety (ASF) • Verilog & SystemVerilog • Digital Design & Verification • Functional Coverage & Debuggings My academic and technical background includes experience in CMOS circuit design, combinational logic design, and hardware verification using industry-standard tools. I am passionate about learning advanced verification methodologies, computer architecture, and next-generation semiconductor technologies. I am always open to connecting with professionals and researchers working in VLSI, PCIe, Functional Safety, and semiconductor design & verification.

Experience

1 mo
Total Experience
1 mo
Average Tenure
1 mo
Current Experience

Cadence

3 roles

Design Engineer I

May 2026Present · 1 mo

PCIe Protocol & VerificationFunctional Safety (ASF)VerilogSystemVerilogDigital Design & VerificationFunctional Coverage & Debugging

Design Verification Engineer

Jul 2025Present · 11 mos

Trainee

Jan 2025Jul 2025 · 6 mos

PCIeFunctional coverage

Education

Manav Rachna Educational Institutions

B.tech — ECE IOT

Jun 2021Jul 2025

SASI JUNIOR COLLEGE

secodary

Apr 2019May 2021

Chalapathi Public School

High School

Jan 2018Jan 2019

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