Srikanth Varma Chakka

Director of Engineering

Hyderabad, Telangana, India16 yrs 8 mos experience

Highly Stable

Key Highlights

20+ years in FPGA/SoC design and verification.
Expert in full chip integration across multiple technology nodes.
Led projects from 250nm to 3nm technology.

Stackforce AI infers this person is a semiconductor design expert with extensive experience in FPGA and SoC technologies.

Contact

Skills

Core Skills

Physical VerificationFull Chip Integration

Other Skills

Team ManagementMask DesignIC layoutMixed SignalDRCFloorplanningVLSIASICSoCCMOSAnalogFPGAPLLApplication-Specific Integrated Circuits (ASIC)Cadence

About

20+ years of experience in driving FPGA/SoCs to tapeout. Full chip integration and physical verification expert. Handled multiple projects with different technology nodes at a time. Have worked from 250nm to 3nm and has exposure to all varieties of full chip layouts.

Experience

16 yrs 8 mos

Total Experience

6 yrs 4 mos

Average Tenure

4 yrs 3 mos

Current Experience

Amd

2 roles

Senior Manager Silicon Design Engineering

Promoted

Jul 2024 – Present · 1 yr 10 mos · Hyderabad, Telangana, India

Physical VerificationFull chip integration

Manager Mask Layout Design

Feb 2022 – Jul 2024 · 2 yrs 5 mos · Hyderabad, Telangana, India

Xilinx

2 roles

IC Layout Engineering Manager

Promoted

Jul 2020 – May 2022 · 1 yr 10 mos

Senior IC Layout Engineer - INTL

Jul 2017 – Jul 2020 · 3 yrs

Microsemi corporation

Staff Engineer

Sep 2009 – Jul 2017 · 7 yrs 10 mos · Hyderabad Area, India

Qualcore logic

Member Technical Staff

May 2005 – Sep 2009 · 4 yrs 4 mos

Started career as Diploma engineer trainee.
Get trained on Chip Fabrication concepts, Perl scripting, Maskdesign using Cadence virtuso layout editor and Verification using calibre.
Worked on all the Analog stuff like PLL, DLL, ADC, DAC, BGB, POR and IOs and special IOs.
And get releaved from position of Member Technical Staff on September 11th 2009.