Sunil Kumar Viyyapu

Software Engineer

Bengaluru, Karnataka, India4 yrs 9 mos experience

Highly Stable

Key Highlights

Experienced STA and Synthesis Engineer at MediaTek.
Strong academic background in VLSI Design and Embedded Systems.
Proficient in key skills like Verilog and Logic Synthesis.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Static Timing Analysis and Logic Synthesis.

Contact

Skills

Other Skills

CLPStatic Timing AnalysisVerilogLogic SynthesisDFT

Experience

4 yrs 9 mos

Total Experience

4 yrs 9 mos

Average Tenure

4 yrs 9 mos

Current Experience

Mediatek

3 roles

Staff Engineer

Jun 2024 – Present · 1 yr 11 mos

Senior Engineer

Jul 2021 – May 2024 · 2 yrs 10 mos

Student Intern

Aug 2020 – Jun 2021 · 10 mos

Education

National Institute of Technology Rourkela

Master of Technology - MTech — VLSI Design and Embedded Systems

Aug 2019 – May 2021

Sathyabama University

Bachelor of Engineering - BE — Electronics and Instrumentation Enginnering

Jan 2013 – Jan 2017

Narayana Junior College, Visakhapatnam

12th Class

Jan 2011 – Jan 2013

St. Aloysius Anglo-Indian High School, Visakhapatnam

Matriculation

Jan 2002 – Jan 2011

Stackforce found 100+ more professionals with CLP & Static Timing Analysis

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