Naveen Kumar T V

Software Engineer

Bangalore Urban, Karnataka, India7 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in block level physical design implementation.
  • Hands-on experience with advanced technology nodes.
  • Proficient in physical verification and timing closure.
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in advanced technology nodes.

Contact

LinkedIn

Skills

Core Skills

Physical DesignTiming ClosurePhysical Verification

Other Skills

Static Timing AnalysisIRPNRCLPSTADRC fixingTiming fixingCLP fixingIR fixingInnovusCalibreTweakerSynthesisLECCadence

About

Hands-on experience in block level physical design implementation from Floorplan to GDSII. Experience in working on 4nm, 6nm and 16nm design. Physical verification – DRC, LVS. Worked on both dynamic and static IR  analysis/fixes.  Experience on performing ECO and timing Closure on Block level. Foreign Consignment: SocioNext, Shanghai, China (From Pozibility) Tool: Innovus,ICC2,Tweaker, Calibre & Prime time

Experience

7 yrs 11 mos
Total Experience
2 yrs 7 mos
Average Tenure
4 yrs 2 mos
Current Experience

Mediatek

Staff physical design Engineer

Feb 2022 – Present · 4 yrs 2 mos · Banglore

Static Timing AnalysisPhysical DesignTiming ClosureIRPNRCLP+2

Silica design

Senior Physical Design Engineer

Sep 2020 – Feb 2022 · 1 yr 5 mos · Bangalore Urban, Karnataka, India

  • Physical design Implimentation from Netlist to GDSII using Innovus. Hands on experiance on closing 6 nm and 4 nm Technology.
  • PNR using INNOVUS, Fixing CLP erros, DRC fixing, timing fixing in Tweaker/PT and IR fixing .
  • Tools: INNOVUS, Calibre , PT, Tweaker.
Physical DesignDRC fixingTiming fixingPNRCLP fixingIR fixing+4

Pozibility technologies pvt ltd

Physical Design Engineer

Jan 2018 – May 2020 · 2 yrs 4 mos

  • Physical Design Implementation from Netlist To GDSII using Innovus. Hands on experience in closing designs at 16nm Technology.
  • client: Socionext China
  • tools: Cadence, ICC2, PT
  • expertise in PD, PV.. hands on STA, Synthesis , LEc
Physical DesignSTASynthesisLECCadenceICC2+2

Tech mahindra

Intern

Aug 2014 – Jul 2015 · 11 mos

Education

S J C Institute of Technology, CHICKBALLAPUR

Master of Technology - MTech — Signal processing

Jan 2013 – Jan 2015

Govt. S K S J Technological Institute, BANGALORE

Bachelor of Engineering - BE

Jan 2009 – Jan 2013

Stackforce found 100+ more professionals with Physical Design & Timing Closure

Explore similar profiles based on matching skills and experience

Indushekhar Benjwal

Indushekhar Benjwal

Director of Engineering

at Intel Corporation

Bengaluru, India27 yrs 1 mo exp
ManagementPDK DevelopmentPhysical ImplementationDesign PortingBackend Design Methodologies
Sridhar Krishnappa

Sridhar Krishnappa

Staff Engineer

at MediaTek

Bengaluru, India8 yrs 3 mos exp
Physical DesignVLSI
SU

Sagar Undale

Senior Manager

at Intel Corporation

Bengaluru, India21 yrs 11 mos exp
Radhika Shankar

Radhika Shankar

Vice President of Applications Engineering

at Synopsys Inc

Fremont, United States30 yrs 9 mos exp
EDAIntegrated Circuit Design
Satish Chandra Dixit

Satish Chandra Dixit

Senior Staff Engineer

at Qualcomm

Noida, India12 yrs 4 mos exp
Static Timing AnalysisCPU designSystem on a Chip (SoC)Low-power DesignTiming Signoff
Shashank Misra

Shashank Misra

Principal physical design Engineer

at Astera Labs

Noida, India16 yrs 1 mo exp
Srujan B V

Srujan B V

STA/ SYNTHESIS Engineer

at MediaTek

Bengaluru, India6 mos exp
Static Timing AnalysisVery-Large-Scale Integration (VLSI)
Abhishek Mujakari

Abhishek Mujakari

MTS Silicon Design Engineer

at AMD

Hyderabad, India7 yrs 4 mos exp
Physical DesignStatic Timing Analysis