Sunkenapally Mallikarjun

Software Engineer

Hyderabad, Telangana, India6 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 4 years of experience in Digital Design.
Recognized for contributions in complex SoC integration.
Awarded for innovative Perl flow development.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and SoC integration.

Contact

Skills

Core Skills

Rtl DesignSilicon Design

Other Skills

Cache HierarchyVerifPDSoCFuse RegistersPerlClock Domain CrossingIntegrationChecker ModulesFirmware SequenceLayoutSynthesisTiming AnalysisPower AnalysisMentoring

About

I have 4+ years of experience in Digital Design. Into RTL design of Cache Hierarchy modules of Zen Architecture design. I have dual master M.Tech (Electronics ) and MA(Public Administration) from IISc and JMI respectively. I was recognized at every organization for my commitment. Though people consider me a slow runner but i believe in Old story of rabbit and tortoise. I have experience of 2 whole project cycles in both RTL and PD domain.

Experience

6 yrs 9 mos

Total Experience

3 yrs 4 mos

Average Tenure

4 yrs 10 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Dec 2023 – Present · 2 yrs 6 mos · Hyderabad, Telangana, India

Responsibilities
RTL Design owner of blocks in Cache hierarchy.
Disposing of issues raised by Verif/PD/SoC
Primary owner of fuse registers and its budgeting across the projects.
Ownership of Firmwear sequence of core complex for Client SoC.

RTL DesignCache HierarchyVerifPDSoCFuse Registers+1

Silicon Design Engineer ll

Jul 2021 – Nov 2023 · 2 yrs 4 mos · Hyderabad, Telangana, India

Recognition:
Quarterly Spot light Award(Q3-2022) for the contribution of creating a perl flow, to address conflict of module name with different functionality at Cache Heirarchy Level.
Quarterly Spot light Award(Q2-2023) for the contribution of supporting critical and complex issues in the integration of Core Complex at SoC for the first of its own kind implementation within AMD.
Responsibilities
RTL Design owner of legacy blocks. Upgraded for relocation of synchronization & LDO modules, optimization of IOs and Bug fixes based on project specifications.
Perl based flow to support first of its own kind of implementation in a multi core-complex design and closely worked with SoC to ease the integration of core complexes.
Primary owner of fuse registers and its budgeting across the projects.
Participated in various PRs to check the feasibility of legacy codes in meeting HLD specifications.
Automated generation of checker modules to achieve the ISA compatibility across multi-variant cores.
Supported in enhancement of Firmwear sequence to reduce bootup time for a multi core design.
Integrated multiple IPs based on project specification without impacting the legacy designs.
Created Perl flow to solve the problem of module name conflicts for a design generated out of a single codeline.
Flow optimization for CDC quality checks by parameterizing the modules.
Ownership of RTL quality checks- lint and CDC across hierarchies.
Mentoring Interns and New hires with the design and flow related aspects.

RTL DesignPerlFuse RegistersClock Domain CrossingIntegrationChecker Modules+2

Intel corporation

Design Engineer

Jul 2015 – Jun 2017 · 1 yr 11 mos · Bangalore Area, India

Responsibilities include RTL to layout which implies design synthesis, floorplan, placement, Clock Tree Synthesis, Static timing Analysis, ECO, Power analysis and optimization, sign-off.
Functional and timing ECO implementation and timing closure of multiple blocks without degrading the qualities of speed paths.
Active participation and contributor in designing Mode of Work and Technical Readiness to support shift and tool setup along the dimensions of power analysis, metal track, DRCs.
Focus laid towards power budget analysis, floor plan and aspect ratio analysis of functional unit block and its route resource congestion.
Miscellaneous Responsibilities
Active participation of technical readiness works like tool chain setup, pre-project impact analysis, Budget analysis.
Mentoring new joinees, freshers and experienced, with internal tools and work flow.
Working closely with interns to empower their knowledge and technical skills to become contributors for the organization.
Active contributor in organizing work-life balance events in organization to promote team spirit.
Recongitions
Received appreciation for handling manually 300+ max-min timing critical complex and congested fubs where automated tools were failing
Recognition award for basic scripts to meet timing requirements in simple to medium fubs which swaps the hvt and svt cells based on the timing slack available.
Received recognition for taking ownership of additional unit to meet the project dead line.